Takao Kashiro

Low-power video encoder/decoder chip set for digital VCRs

Since low-power battery operation is essential for a portable VCR with video camera, the complex computation of MPEG2 encoding is not suitable for consumer digital VCR. This implementation of the video codec using compression optimized for LSI has more than an order of magnitude lower power consumption than that of recently-reported MPEG2 codecs. Power-saving modes and 0.5 /spl mu/m 2 V CMOS standard-cell library also reduce power. Two chips, Shuffling LSI and Compression LSI, together with a 5 Mb DRAM, can either encode the CCIR601 digital component video signal into the standard-definition digital VCR (DVCR) format or decode the DVCR format signal into a component video signal.

The development of audio and video signal processing LSI for SD-DVC

The internal bus architecture for a consumer-use digital VCR is described. The system is optimized so that a system with a digital interface function can be easily constructed. This architecture has the flexibility for the other applications. >

The development of audio and video signal processing LSI for digital VCR

Signal processing LSIs conforming to the specifications of a consumer-use digital VCR have been developed. A higher compression mode and flexibility of the signal processing are addressed.