Takao Miyazaki

Self-aligned transistor with sidewall base electrode

This report will cover a multiple-self-aligned bipolar structure with negligible parasitic junction capacitances, suitable for scaled-down I²L-VLSI. A fabricated model indicared that C<inf>CB</inf>was reduced by 75% and β<inf>u</inf>and β<inf>d</inf>was increased 4 times compared to a conventional structure.

Self-Aligned Transistor with Sidewall Base Electrode

A multiple self-aligned structure that facilitates high packing density and high speed in bipolar VLSIs is proposed. The device has polysilicon sidewall base electrodes to reduce parasitic junction capacitances. The new devices indicate that capacitances between the base and collector regions are reduced to 1\4 and the ratio of reverse-to-forward current gain is increased about 5 times that of conventional bipolar transistor structures, and gate delay in IIL circuits is about 1 ns/gate. The structure opens the way for further scaled-down VLSI.

Electrical Properties of Gallium Arsenide-Insulator Interface

Gallium arsenide-insulator interface properties were investigated from an analysis of conventional characteristics of MIS structures. Energy distributions of interface state density were U shape having minimum values near the mid-gap energy. The values of minimum density were dependent upon conduction types of substrates and deposition conditions of insulator films but independent of crystal orientations. They were from 0.9 to 20×1011 cm-2 eV-1 for p-type substrate and from 1 to 4×1012 cm-2 eV-1 for n-type substrate. An anomalous frequency dispersion of capacitance was observed in the accumulation region on n-type substrate and was explained by deep traps formed by oxygen atoms doped during oxide film deposition.N-channel GaAs-MISFETs were fabricated and the maximum field effect mobility of electron in the inversion layer was 1480 cm2 V-1 sec-1.

High-Speed IIL Circuits Using a Sidewall Base Contact Structure

New high-speed self-aligned IIL structures with 3 µm × 3 µm collectors that produce minimum gate delays of 290 ps/gate(fanout is 1) and power delay products of 15 fJ/gate at low injector current levels are described. Maximum toggle frequency in an IIL T-type flip-flop is measured at 5 mW and found to be up to 315 MHz.

On the Tunneling Current through Thin Aluminum-Oxide Films

The mechanism of the electrical conduction in a metal-insulator-metal thin film diode is discussed by the tunneling process. Experimental current-voltage characteristic and its temperature dependence of an Al-Al oxide-Al diode agree well with a theoretical calculation when the potential barrier is assumed to have a geometrically simple shape. Practical barrier height of the diode is estimated at 2.2 eV from a photosensitive measurement. Electrode effects are also discussed from the viewpoint of rectification. The surface potential of the insulator on Al film is measured to be 3.6 eV, which is consistent with a simple potential diagram of the metal and insulator surfaces.

Integrated 84ps ECL with I 2 L

A side wall base contact structure used to fabricate 84ps ECL and 320ps I²L circuits with gate areas of 3500μm²and 112μm²will be covered.

High-speed IIL circuits using a sidewall base contact structure

New high-speed self-aligned IIL structures with 3 µm × 3 µm collectors that produce minimum gate delays of 290 ps/gate(fanout is 1) and power delay products of 15 fJ/gate at low injector current levels are described. Maximum toggle frequency in an IIL T-type flip-flop is measured at 5 mW and found to be up to 315 MHz.

Rapid-thermal annealing of a polysilicon-stacked emitter structure

Second-duration rapid-thermal annealing technique is applied to an As drive-in process from a stacked CVD poly-Si film for shallow emitter formation. Highly effective dopant activation, especially in the stacked film, can be achieved without deep As diffusion into the substrate. Transformation of the poly-Si film into single crystal through a kind of secondary recrystallization, i.e., epitaxial grain alignment is a substantial cause for effective activation in the film. High-frequency bipolar transistors with rapid-annealed emitters are demonstrated in comparison with conventionally processed ones to show technique feasibility.

290 psec I 2 L circuits with five-fold self-alignment

New, high speed, self-aligned IIL structures with minimum gate delays of 290 psec/gate(fanout=1) and power delay products of 30 fJ/gate at low injector current levels with 3 µm × 3 µm collectors are demonstrated. Maximum toggle frequency in an IIL T-type flip-flop is measured at 2 mW and found to be up to 220 MHz.

Two signals in electrically detected magnetic resonance of platinum-doped silicon p–n junctions

We have found two electrically detected magnetic resonance (EDMR) signals at room temperature in forward-biased platinum (Pt)-doped (111) silicon p–n junction diodes with a linearly graded junction. The g values of the two EDMR signals are 1.991 (signal 1) and 1.978 (signal 2), respectively, when the surface of the diode is parallel to the magnetic field. The two signals increase after applying a large reverse-bias voltage to the junction. They decay with time; the decay rate after more than 1 h is smaller for signal 1 than for signal 2. The recombination current also changes in a similar manner as the EDMR signals. The intensity of the two EDMR signals each shows a known bell-shape dependence on a forward bias voltage; signal 1 is observed at slightly lower voltages than signal 2. The deep level transient spectroscopy (DLTS) spectrum from the diodes shows two peaks at 0.23 and 0.32 eV. For diodes with different Pt-diffusion temperatures, 865 and 885 °C, the ratio of the intensity of the EDMR signals corr...