Takao Waho

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

Low-power successive-approximation (SA) analog-to-digital converters (ADCs) are attracting increasing attention these days in biomedical and sensor network applications. The binary search algorithm is one of the basic idea behind how they obtain a binary code representing an analog input. In practice, the imperfectness of analog circuit elements sometimes results in decision errors and decreases the resolution of A/D conversion. Thus, making accurate decisions using imperfect elements is a big challenge. This paper surveys one solution known as non-binary SA with redundancy as well as related topics and its application to state-of-the-art SA ADCs.

Energy Efficiency of Multi-bit delta-sigma Modulators Using Inverter-based Integrators

Energy efficiency of multi-bit ΔΣ modulators has been investigated in terms of a normalized power dissipation, which is commonly referred to as the figure-of-merit (FOM). The multi-bit modulators are designed by adding a multi-level comparator and feedback path to a conventional inverter-based modulator. The FOM is estimated by transistor-level circuit simulation assuming a 0.18-μm standard CMOS technology. In the present 3-bit modulator, the FOM is improved by more than a factor of two compared with a conventional 1-bit one. By using the multi-level comparator, the smaller quantization error reduces the settling time in the integrators, and then improves the energy efficiency.

A low-distortion switched-source-follower track-and-hold circuit

A novel switched-source-follower track-and-hold (T/H) circuit has been proposed, where an input source-coupled pair conventionally used preceding the source-follower switch is replaced with another source-follower stage. Suppressing signal-dependent sample-timing jitter, which is due to the channel-length modulation of the input transistor, leads to a low-distortion T/H operation. Circuit simulation assuming a 0.1-μm InP-based HEMT technology has revealed an SFDR improvement from 58dB to 70dB for input and sampling frequencies of 3 GHz and 20 GHz, respectively. Although the present result is based on the high-speed compound semiconductor technology, the idea behind this can be applied to T/H circuits using nano-scale MOSFETs with reduced output impedance.

A Low-Power Successive Approximation Analog-to-Digital Converter Based on 2-Bit/Step Comparison

A novel low-power 8-bit successive approximation (SA) ADC using multiple-valued approach is presented. In contrast to conventional 1bit/step SA ADCs, 2bit/step conversion is employed, and combined with the split capacitor array and dual sampling technique to reduce the power consumption. Transistor level simulation, assuming 0.18-µm standard CMOS technology, shows that the total power consumption decreases by about 20% compared with that obtained for a 1bit/step counterpart at a sampling frequency of 100 kHz. Since the digital part consumes more power than the analog part, the present approach is expected to be more attractive for ADCs using advanced process technology.

Enhancement of comparator operation speed by using negative-differential-resistance devices

Enhancement of comparator operation speed by using negative-differential-resistance (NDR) devices has been investigated. A clocked comparator including resonant-tunneling diodes (RTD) as the NDR devices as well as high-electron-mobility transistors (HEMT) is designed. Theoretical analysis based on equivalent circuits and transistor-level circuit simulation are carried out to estimate the regeneration and recovery times, as figures of merit, It is found that the regeneration time is reduced by 50% by using the RTDs, while the recovery time remains almost at the same value.

On the temporal behavior of dc and rf characteristics of InAs nanowire MISFET

Nanowire devices have drawn increasing attention as one of the most promising candidates for logic switches. Recently; III–V nanowire MISFETs have been fabricated exhibiting extremely high transconductance [1, 2]. However, there are only a very few works on their applicability in high speed monolithic integrated circuits [3–5]. In this contribution, the temporal behavior of their dc and rf characteristics has been studied as a prerequisite for the set-up of reliable device models.

A Successive Approximation A/D Converter Using Generalized Non-Binary Algorithm

An 8-bit successive approximation analog-to-digital converter (SA ADC) has been designed and fabricated by using a 0.18-μm technology. A generalized non-binary algorithm has been used to enhance operation speed by relaxing the settling constraint of the DAC output. A split-capacitor array with a monotonic switching scheme has also been incorporated to reduce the power consumption. Transistor-level simulation shows an effective number of bits (ENOB) of 7.91 bits under a Nyquist condition with a sampling frequency of 2 MHz. Fabricated chip operates successfully, proving the design principle.

An experimental 4RTD logic gate

A novel logic circuit using resonant-tunneling diodes (RTD), called a 4RTD logic gate, was proposed recently, and possible 200-GHz AND/OR and NAND/NOR operations were predicted by circuit simulations [Yamada,2005]. This paper presents, for the first time, experimental results of the 4RTD logic gate. In particular, an experimental current-mode AND gate has been successfully demonstrated

Heterogeneous integration of an InAs nanowire with energy-efficient CMOS delta-sigma modulator

A nanowire-CMOS heterogeneously integrated circuit is demonstrated. The circuit consists of a voltage divider using series-connected resistors and a delta-sigma modulator (DSM); a single InAs nanowire is used as one of the resistors. Nanowire deposition is carried out by field-assisted self-assembly (FASA) process based on dielectrophoresis. The DSM uses a class-C inverter in its loop filter instead of an opamp to obtain high energy efficiency, and successfully converts the voltage across the nanowire into density-modulated digital pulses. The present result suggests that variations in the nanowire resistance caused, for example, by chemical absorption on the nanowire surface can be sensed and converted into the digital output.

An energy-efficient ΔΣ modulator using dynamic-common-source integrators

An energy-efficient ΔΣ modulator has been investigated by using dynamic-common-source integrators. Instead of the virtual short commonly used in conventional opamp-based integrators, the novel integrator used the fact that when a MOSFET turns off from its on-state, the voltage difference between the gate and source approaches to the threshold voltage, which is virtually constant after the charge redistribution. No static currents flow in the present integrator, resulting in high energy efficiency. An FOM of 29 fJ/comv-step was estimated by our transistor-level circuit simulation assuming a 0.18-μm standard CMOS technology with an SNDR, a bandwidth and a sampling frequency of 82.6dB, 20 kHz and 5 MHz, respectively.