Takashi Sakurada

On the frequency dependent drain conductance of ion-implanted GaAs MESFETs

The effect of MESFET structure on the frequency dispersion of drain conductance (g/sub d/) was examined, It was found that a shorter gate length, lower buried p-layer concentration, lower sheet resistance of n/sup +/ layer, and thinner active layer thickness are effective in suppressing the frequency dependent g/sub d/. These phenomena are explained by the presence of deep traps in the depletion layer between the semi-insulating substate and active layer. We also show that the cross-point change of eye-pattern for density of input signal in logic ICs is due to frequency dependent g/sub d/ The cross-point change between mark ratio of 1/8 and 7/8 shows a linear relationship with gd/sub RF//gd/sub dc/ (the ratio of the drain conductance at RF and dc input), These results indicate that an optimized device structure with g/sub d/ small frequency dispersion can be used to realize high-speed and high quality logic ICs.

4-inch Fe-doped InP substrates manufactured using vertical boat technique

Recent progress of high speed optical communication systems have been increasing the fabrication scale of devices, such as HBTs and OEICs. These devices will require semi-insulating Fe-doped InP substrates that are larger in diameter (4-inch) and higher in quality to improve device performance and reduce costs. With the growth of larger diameter InP crystals the increase of dislocation densities becomes critical. Though a boat growth method is the most appropriate for achieving low dislocation density, the boat growth of InP is difficult because of twinning issues. Therefore, most previous efforts have adopted a < 111 >-orientation to prevent twinning. However, this type of orientation is not suitable for the production of [100] substrates. SEI has succeeded in developing 4-inch Fe-doped InP substrates that are higher in quality using our VB (Vertical Boat) technique.

Improvement of microscopic and macroscopic uniformity in 4-inch InP substrate for IC application by vertical boat growth

Macroscopic and microscopic uniformity in 4-inch InP substrates has been significantly improved by new developments in SEIs Vertical Boat (VB) technique. In this paper, we report improvements, in etch-pit density (EPD) distribution, micro-resistivity profiles, and photoluminescence (intensity and 4.2K spectra), for 4-inch InP VB in comparison to both VCZ (SEI proprietary Vapor pressure controlled Chockralski) and commercially available VGF substrates.

Novel RTA technique for large diameter GaAs wafers managing to minimize both dopant diffusion and slip formation

Rapid thermal annealing (RTA) is useful for shallow channel device fabrication because of suppression of dopant diffusion. However, short RTA sequence easily causes slip formation due to thermal stress during the process, which is more serious in the case of larger diameter wafers. We investigated at what point slip generated during RTA by monitoring temperature distribution within a wafer and successfully suppress slip formation by introducing a waiting step in the cooling process while maintaining the high cooling rate and the abrupt doping profile.