Takefumi Yoshikawa

A 125–1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

A process-independent adaptive bandwidth spread-spectrum clock generator (SSCG) with digitally controlled self-calibration techniques is proposed. By adaptively calibrating the VCO gain (Kv) and charge-pump (CP) current over C (ICP/C), the SSCG can realize not only adaptive bandwidth but also process independence at each operating frequency. The innovative point is the adaptive bandwidth control using Kv and ICP/C calibration. This control enabled a test chip to keep a sharp triangular SSC profile while operating over a wide frequency range (125 to 1250 MHz). The variations of VCO gain and CP current are reduced to one third those of the conventional architecture. At 1250 Mbps (625 MHz) the reduction of spectrum peak amplitude is 18.6 dB which is 2.3 dB better than the reduction obtained without calibration.

Design of Simultaneous Bi-Directional Transceivers Utilizing Capacitive Coupling for 3DICs in Face-to-Face Configuration

Capacitive-coupling-based simultaneously bi-directional transceivers for chip-to-chip communication in three-dimensional integrated circuits are presented. By employing a 4-level signaling strategy with a novel cascaded capacitor configuration, the proposed transceivers can transmit and receive data simultaneously through a single inter-chip coupling capacitor, and effectively improve the throughput per interconnect. In this work, the proposed cascaded capacitor structure and its signaling strategy are discussed in details and circuit solutions for transceivers are presented. A parasitic shielding technique is employed in the electrode design to improve signal swings without area overheads. A 16μm×20μm electrode provides the voltage margin as large as 195 mV at 1.2 V supply (verified by post-layout simulation) for signal sensing and recovery. The proposed transceivers are designed in a commercial 65-nm complementary metal-oxide-semiconductor technology.

A Spread Spectrum Clock Generator Using Digital Tracking Scheme

A Spread Spectrum Clock Generator (SSCG) using Digital Tracking scheme (DT-SSCG) is described. Using digital tracking control outside a PLL, DT-SSCG can realize stable modulation characteristic independent of the PLL constants. Moreover, DT-SSCG can apply to various modulation profiles easily by brief change of the digital tracking parameters. A test chip has realized the fitting of 5000 ppm downspread with 6.02 dB and 8.02 dB spectrum peak reduction for triangle and Non-Linear modulation.

An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics

This paper describes an area-effective 1.5-Gb/s transceiver core with spread spectrum clocking (SSC) capability that is suitable for integration into large system-on-chips (SoCs) for consumer electronics applications such as audio and video stream data transmission. To achieve a good balance between SSC performance and the core area, a novel SSC scheme using a multi-level (hierarchical) phase-interpolator technique has been developed. This technique achieves a very fine clock phase shift of about 0.1 ps for precise and smooth frequency modulation. The SSC scheme is based on a digital feed-forward operation and leads to a small area and good noise robustness for SoC integration. This core also has digital clock data recovery (CDR) with jitter tolerance enhancement and a simple adaptive data equalizer (AEQ). These functions are also on a digital operation and controlled by digital codes, and the core presupposes a multiphase clock for the digital SSC, CDR, and AEQ with shared phase-locked loop (PLL) topology. A test chip including two of these cores was fabricated using shared PLL. The core showed significant peak power reduction (-19 dB to the non-SSC situation) and a small core area of 0.25 mm2 in 0.13-mum CMOS process. This core achieved a remarkable ratio of peak power reduction to area of 76 dB/mm2. Moreover, it achieved good jitter tolerance (flat 0.8 UI at >1 MHz) and stable data communication over an STP (shielded twist pair) cable ranging in length from 1 m to over 22 m.

A 5 Gbps CMOS frequency tolerant multi phase clock recovery circuit

A clock and data recovery (CDR) circuit using multi phase gated VCO (MGVCO) technique for multi-channel high-speed serial interface was developed. This architecture can realize quick data acquisition and plesiochronous clocking capability. A 5 Gbps 32-channel test chip, designed in 0.18 /spl mu/m CMOS technology, achieved BER of <10/sup -12/ in 5 Gbps CDR operation with /spl plusmn/3% frequency tolerance for random incoming data of 2/sup 7/-1.

A 3-Gb/s/ch Simultaneous Bidirectional Capacitive Coupling Transceiver for 3DICs

This brief presents a simultaneous bidirectional capacitive coupling transceiver for intertier communication in 3-D integrated circuits. A novel capacitive coupling interconnect structure is proposed. Optimization of the proposed interconnect structure for minimizing parasitic capacitance achieves the voltage swing VSW of 200 mV at the voltage sensing nodes. The data rate of 3 Gb/s/ch is demonstrated in the emulated-3D interconnect. The proposed transceiver consumes 140 μW at 3 Gb/s/ch. The test chip was fabricated in a 65-nm CMOS technology.

Design of self-biased fully differential receiver and crosstalk cancellation for capacitive coupled vertical interconnects in 3DICs

Interconnect density in traditional capacitive coupling electrodes array is limited by capacitive crosstalk between electrodes. In this work, we propose an array structure where single-ended and differential pair electrodes (designed in the common-centroid structure) are alternatively placed horizontally and vertically. The proposed structure not only cancels out the crosstalk noise but also reduces the spacing requirement between electrodes. A novel self-biased fully differential receiver suppresses the common-mode coupled crosstalk in the differential electrodes. The receiver provides CMRR of 25dB and can recover wide band (10 kHz ~ 1 GHz) signals with 32dB gain. It consumes 25 μW at 1 GHz. It is designed and simulated in a 1.5V 0.13μm CMOS technology.

2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D Integration

This paper introduces a hybrid capacitive coupling interconnects (CCIs) array suitable for bumpless flip-chip 3-D integration. Inside the hybrid array, both single-ended and common-centroid differential CCIs are interleaved together to cancel the crosstalk among them. The crosstalk cancellation capability of its own allows CCIs to be placed closer and thus improves the area efficiency. A high gain and high common-mode-rejection ratio receiver is also presented to minimize the jitter caused by the common-mode noise. The process variation track biasing circuit is also proposed for the receiver. The measurement verifies that the proposed transceiver in a 3 × 3 pseudohybrid CCIs array produces only 84 ps or 0.2 unit interval crosstalk related jitter under the worst case crosstalk condition. A total of nine transceivers in the array achieve the data rate of 20.79 Gb/s and consume only 53 μW/Gb/s. The chip was fabricated in 65-nm CMOS technology.

An ultra-wide range Bi-directional transceiver with adaptive power control using background replica VCO gain calibration

A novel transceiver with adaptive power control (APC) using a process and frequency monitor (PFM) based on a new adaptive power optimization concept is proposed. The PFM employs gain calibration with a replica VCO and operates in the background. A test chip, employing adaptive amplitude scaling (AAS), adaptive bias scaling (ABS), and adaptive supply-voltage scaling (AVS), achieved adaptive power over a wide frequency-range (0.05–3.4Gbps). At 100Mbps the measured power with APC was reduced by 75% compared to conventional architecture without APC.

Yield Enhancement of Face-to-Face Cu–Cu Bonding With Dual-Mode Transceivers in 3DICs

When more than one dies are stacked vertically in 3-D integrated circuits (3DICs), the overall system yield degrades significantly. While each die can be tested before stacking, failures in 3DIC interconnects could jeopardize the entire system. In this paper, a dual-mode transceiver is proposed as a built-in-self-test/repair solution to improve the yield of direct face-to-face copper thermocompression bonding (Cu–Cu bonding). The proposed transceiver could improve the Cu–Cu bonding-based interconnect reliability with the introduction of two operation modes: the ohmic mode when Cu–Cu bonding presents low resistance and the capacitive coupling mode when Cu–Cu bonding is showing any sign of failure with high resistance at the bonding interface. Such mode sensing is self-contained in the transceiver itself with the help of the proposed resistance sensor. In this paper, we discuss the modeling of Cu–Cu bonding and the proposed transceiver design with power, latency, jitter, and crosstalk simulations followed by the design guideline for the practical implementation with yield analysis.