Tsuyoshi Ebuchi

A 125–1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

A process-independent adaptive bandwidth spread-spectrum clock generator (SSCG) with digitally controlled self-calibration techniques is proposed. By adaptively calibrating the VCO gain (Kv) and charge-pump (CP) current over C (ICP/C), the SSCG can realize not only adaptive bandwidth but also process independence at each operating frequency. The innovative point is the adaptive bandwidth control using Kv and ICP/C calibration. This control enabled a test chip to keep a sharp triangular SSC profile while operating over a wide frequency range (125 to 1250 MHz). The variations of VCO gain and CP current are reduced to one third those of the conventional architecture. At 1250 Mbps (625 MHz) the reduction of spectrum peak amplitude is 18.6 dB which is 2.3 dB better than the reduction obtained without calibration.

A Spread Spectrum Clock Generator Using Digital Tracking Scheme

A Spread Spectrum Clock Generator (SSCG) using Digital Tracking scheme (DT-SSCG) is described. Using digital tracking control outside a PLL, DT-SSCG can realize stable modulation characteristic independent of the PLL constants. Moreover, DT-SSCG can apply to various modulation profiles easily by brief change of the digital tracking parameters. A test chip has realized the fitting of 5000 ppm downspread with 6.02 dB and 8.02 dB spectrum peak reduction for triangle and Non-Linear modulation.

An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics

This paper describes an area-effective 1.5-Gb/s transceiver core with spread spectrum clocking (SSC) capability that is suitable for integration into large system-on-chips (SoCs) for consumer electronics applications such as audio and video stream data transmission. To achieve a good balance between SSC performance and the core area, a novel SSC scheme using a multi-level (hierarchical) phase-interpolator technique has been developed. This technique achieves a very fine clock phase shift of about 0.1 ps for precise and smooth frequency modulation. The SSC scheme is based on a digital feed-forward operation and leads to a small area and good noise robustness for SoC integration. This core also has digital clock data recovery (CDR) with jitter tolerance enhancement and a simple adaptive data equalizer (AEQ). These functions are also on a digital operation and controlled by digital codes, and the core presupposes a multiphase clock for the digital SSC, CDR, and AEQ with shared phase-locked loop (PLL) topology. A test chip including two of these cores was fabricated using shared PLL. The core showed significant peak power reduction (-19 dB to the non-SSC situation) and a small core area of 0.25 mm2 in 0.13-mum CMOS process. This core achieved a remarkable ratio of peak power reduction to area of 76 dB/mm2. Moreover, it achieved good jitter tolerance (flat 0.8 UI at >1 MHz) and stable data communication over an STP (shielded twist pair) cable ranging in length from 1 m to over 22 m.

An ultra-wide range Bi-directional transceiver with adaptive power control using background replica VCO gain calibration

A novel transceiver with adaptive power control (APC) using a process and frequency monitor (PFM) based on a new adaptive power optimization concept is proposed. The PFM employs gain calibration with a replica VCO and operates in the background. A test chip, employing adaptive amplitude scaling (AAS), adaptive bias scaling (ABS), and adaptive supply-voltage scaling (AVS), achieved adaptive power over a wide frequency-range (0.05–3.4Gbps). At 100Mbps the measured power with APC was reduced by 75% compared to conventional architecture without APC.

An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration

A transceiver with adaptive power control using a process and frequency monitor (PFM) is proposed. The PFM employs gain calibration with a replica voltage-controlled oscillator (VCO) and operates in the background. A five-bit digital code detected by the VCO gain calibration is applied to an adaptive-amplitude driver, an adaptive-bandwidth receiver, and an adaptive-bandwidth phase-locked loop. A test chip was fabricated in a 110-nm CMOS process and achieved adaptive power control over a wide frequency range (0.05 to 3.4 Gb/s). At data rate of 100 Mb/s, the measured power consumption attained with adaptive power control was 75% lower than that attained with a conventional architecture without adaptive power control.

Transceiver Macro with Spread-Spectrum Clocking Capability for AC-Coupled Cable Interfaces

A transceiver macro for high-speed data transmission via cable in vehicles is proposed. The transceiver uses ac coupling and bidirectional interface topology for protecting LSIs against unexpected short of cable and harness/chassis and has a spread-spectrum-clocking (SSC) generator that reduces noise due to electromagnetic interference. A driver current control has been used for fast switching of data direction on accoupled interfaces. An adaptive bandwidth control has been used in a ΔΣ PLL to improve SCC significantly. A test chip has been fabricated and shows stable and bi-directional data communication with data rate of 162 to 972 Mbps through 20-m cable. Thanks to an optimum calibration of the SSC-PLL bandwidth, it reduces peak power at 33kHz by -23dB and provides 2% modulation at a data rate of 810Mbps.

An 800 Mb/s physical layer LSI with hybrid port architecture for consumer electronics networking

A physical layer LSI has one DS-port and two /spl beta/ports in accordance with IEEE1394-2000 and P1394b Draft 1.01 respectively. The 0.25 /spl mu/m CMOS LSI realizes 800 Mb/s and 1.2 km peer-to-peer IEEE1394 networking through /spl beta/port. Each /spl beta/port requires 180 mW active power and is treated as ASIC macro for future large system integration.

A 1.25 Gb/s CMOS receiver core with plesiochronous clocking capability for asynchronous burst data acquisition

To realize GB/s data acquisition while suppressing EMI problems, multiport (parallel) optical interconnection is desired. In multiport optical interconnections, a CMOS receiver core in the receiver (which receives serial data from PD array and amplifier) must have (i) >1 Gb/s data acquisition capability with clock recovery for reception of long data streams, (ii) asynchronous burst data acquisition capability to avoid complicated data modulation, (iii) low power dissipation required for multiport receiver LSIs. The authors present a prototype chip, which is fabricated in a 0.25 /spl mu/m CMOS process, to implement these requirements.