Takeki Yazaki

Power Efficient Approach and Performance Control for Routers

We introduce two approaches for power saving routers, which are the power efficient designing and the power saving designing. Power efficient designing enables a high performance router at low power consumption. As a part of power efficient designing, we have integrated ASICs/FPGAs of routers and developed a scalable central architecture. Additionally, we used new high speed memories and high speed interfaces such as a SerDes. As a result, the whole power consumption of our router adopting power efficient designing was reduced over 50% compared to conventional routers. Power saving designing is an approach to cut down wasted power consumption. Two major aspects belong to power saving designing, which are static performance control and dynamic performance control. We have been studying on static performance control, such as power cutting technology per port or module, and power saving mode by frequency switching. We were successful in saving 10-20% of power compared to conventional routers using this power saving mode by frequency switching. Furthermore, we introduce the dynamic performance control as a promising power saving approach for next generation routers. The router controls its performance dynamically according to the amount of received traffic. We show two technologies needed for this approach, which are the dynamically performance controllable router architecture/circuit, and the traffic monitoring/predicting technology. We consider that working on these technologies will save more power.

Technologies to Save Power for Carrier Class Routers and Switches

In this paper, future requirements we believe that will be needed for achieving power efficient routers are shown. The optical backplane is a proposal technology we are working on, which enables a high-speed and power efficient data transmission in backplane of routers and switches, by connecting the electronic devices together with optical paths. It is effective for edge routers and switches which are growing in size with very large throughput that need heavy clustering. According to our estimation, the power efficiency will improve for around 20 percent in total; power consumption in routers. Dynamic performance control is a technology in the system layer. By controlling the performance of the router or switch according to the amount of traffic, the power that is cast away will be decreased. The combination of these technologies will improve the power efficiency for routers and switches.

High-speed IPv6 router/switch architecture

To construct a high-speed and reliable IPv6 network that supports an information society, a high-speed router and switch architecture and new quality of service (QoS) control mechanisms have been developed. The architecture that adopts distributed hardware engines for IPv4 and IPv6 packets achieves wire-rate forwarding for 10 gigabit Ethernet. The QoS control mechanisms, by controlling hierarchical bandwidths, can guarantee the communications of important data such as mission critical data for each network user, assuring bandwidths for each user. A next generation router (GR4000) and a switch (GS4000) based on this architecture provide 320 Gbps maximum capacity with the QoS control mechanisms as well as flow filtering and flow-statistics collection.

Large scale enterprise ATM node with per-VC traffic control

Abstract On the backbone nodes of enterprise networks which handle data and voice traffic, complicated Quality of Service (QoS) capability, transmission efficiency, and high reliability are required. ATM technology satisfies those requirements. We have developed a large scale enterprise ATM node based on the shared buffer switch architecture. In the node, per-VC traffic control functions are implemented at low cost using centralized control of buffer write and read. In this paper, we explain the detail of the per-VC traffic control functions and show the performance results of ABR control using the node.

New bandwidth-control design: policer for probable packet discard (PPPD)

A new bandwidth-control design - called policer for packet probable discard (PPPD) - has been developed. This not only limits the bandwidth of each user to a policing bandwidth, but also achieves TCP throughputs equal to the policing bandwidth. The proposed PPPD uses an improved leaky bucket algorithm, by which packets are discarded at a certain probability when the received bandwidth is judged to be more than the policing bandwidth. Simulations show that the proposed PPPD increases TCP throughput from 74% to 95%, or more, of the policing bandwidth.

Evaluation of a Hierarchical Shaper as a Policy Execution Point

The Next Generation Network (NGN) is expected to become the most important infrastructure for various services used for e-Business such as telephone services, Internet services and new generation broadcasting services. It is supposed to be integrated into all IP network. To satisfy various Quality of Service (QoS) requirements of these services not only for each service but also for every user, we have developed a hierarchical shaper. The shaper has been implemented in a QoS aware gigabit router environment. Although this shaper has to be evaluated to manage actual traffic, the influence of various network conditions on bandwidth control has not been studied thoroughly. This paper reports some experimental results and clarifies the characteristics of the shaper.