Hidetaka Aoki

A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

In the near future, the ability to solve combinatorial optimization problems will be a key technique to enable the IoT era. A new computing architecture called Ising computing and implemented using CMOS circuits is proposed. This computing maps the problems to an Ising model, a model to express the behavior of magnetic spins, and solves combinatorial optimization problems efficiently exploiting its intrinsic convergence properties. In the computing, “CMOS annealing” is used to find a better solution for the problems. A 20k-spin prototype Ising chip is fabricated in 65 nm process. The Ising chip achieves 100 MHz operation and its capability of solving combinatorial optimization problems using an Ising model is confirmed. The power efficiency of the chip can be estimated to be 1800 times higher than that of a general purpose CPU when running an approximation algorithm.

24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing

In the near future, the performance growth of Neumann-architecture computers will slow down due to the end of semiconductor scaling. Presently a new computing paradigm, so-called natural computing, which maps problems to physical models and solves the problem by its own convergence property, is expected. The analog computer using superconductivity from D-Wave [1] is one of those computers. A neuron chip [2] is also one of them. We proposed a CMOS-type Ising computer [3]. The Ising computer maps problems to an Ising model, a model to express the behavior of magnetic spins (the upper left diagram in Fig. 24.3.1), and solves the problems by ground-state search operations. The energy of the system is expressed by the formula in the diagram. Computing flows are expressed in the lower flow chart in Fig. 24.3.1. In the conventional Neumann architecture, the problem is sequentially and repeatedly calculated, and therefore, the number of computing steps drastically increases as the problem size grows. In the Ising computer, in the first step, the problem is mapped to the Ising model. In the next steps, an annealing operation, the ground-state search by interactions between spins, are activated and the state transitions to the ground state where the energy of the system is minimized. The interacting operation between spins is decided by the interaction coefficients, which are set to each connection. Here, the configuration of the interaction coefficients is decided by the problem, and therefore, the interaction coefficients are equivalent to the programming in the conventional computing paradigm. The ground state corresponds to the solution of the original problem, and the solution is acquired by observing the ground state. The interactions for the annealing are performed in parallel, and the necessary steps for the annealing are smaller than that used by a sequential computing, Neumann architecture. As the table in Fig. 24.3.1, our Ising computer uses CMOS circuits to express the Ising model, and acquires the scalability and operation at room temperature.

Spatial computing architecture using randomness of memory cell stability under voltage control

A new computing architecture based on a ground-state search of the Ising model and the probabilistic behavior of a memory cell is proposed. To improve computer performance, a spatial computing architecture that defines an Ising model as the interface between software and hardware is proposed. Various problems can be represented as a spatial parameter in the Ising model. A memory-cell-array-based hardware is utilized to search for the ground state of the Ising model. The interaction between memory cells produces a state transition to lower energy, and the randomness of memory-cell stability at lower voltage helps escape from a local minimum. It was verified by simulation that the proposed architecture can solve practical problems such as factorization and the traveling-salesman problem.

Uncertain behaviours of integrated circuits improve computational performance

Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance.

A powerful yet ecological parallel processing system using execution-based adaptive power-down control and compact quadruple-precision assist FPUs

This paper reports the first trial in which spatially and temporally fine-grained power-down control has been implemented in a high-performance processor in the sense that the FPUs are controlled spatially and dynamically based on the execution sequence.

Design and Power Performance Evaluation of On-Chip Memory Processor with Arithmetic Accelerators

In this paper, we design an on-chip memory processor with arithmetic accelerators, which are expected to improve power consumption. In addition, we evaluate the power performance of the processor. We propose implementing vector-type arithmetic accelerators and SIMD-type arithmetic accelerators in the on-chip memory processor. The evaluation results obtained using our simulator indicate that the performance of the 4FMAs SIMD-type accelerators is similar to that of the 4FMAs vector-type accelerators on DAXPY, Livermore kernel 1 and 3. However, the performance of the 4FMAs vector-type accelerator exceeds that of the 4FMAs SIMD-type accelerator with respect to matrix multiplication and QCD because of difference in element size of the registers. On Livermore kernel 7, the power performance of the 4FMAs SIMD-type accelerators exceeds that of the 4FMAs vector-type because of register reuse. However, the 16FMAs vector-type accelerators have an advantage in almost all simulations, excluding main memory bandwidth intensive benchmarks.

An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution

We developed an SRAM-based CMOS LSI chip that accelerates ground-state searches of an Ising model. Escaping local minima is a key feature to create such a chip. We describe a novel method to escape the local minima by distributing random pulses asynchronously. The random pulses are input from outside of the chip and propagated through two asynchronous paths. In an experiment using a prototype chip, the method achieved the same solution accuracy as the conventional method. In addition, the solution accuracy was further improved by dividing the random pulse distribution path and by increasing the number of pseudo random number generators (PRNGs).

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A carrier-injection-type silicon optical switch (OSW) monolithically integrated with germanium photodiodes (Ge-PDs) is proposed and operated at a wavelength of 1310 nm. The Ge-PDs used for monitoring photocurrent achieve stable switching control. A 4 × 4 silicon OSW, ideally a path-independent-loss type, was fabricated on a silicon-on-insulator substrate. Measured loss variations of all 16 paths were ~3 dB, and the switching response of the OSW was faster than 10 ns. Feedback control of injection current of the OSW was demonstrated. This result shows that the proposed closed-loop feedback control by monitoring photocurrents of Ge-PDs has the potential for stable operation of matrix OSWs.