Takeshi Onomi

Superconducting Neural Network for Solving a Combinatorial Optimization Problem

We propose a neural network using coupled-SQUIDs to solve the N-Queens problem, a combinatorial optimization problem. The N-Queen problem consists of placing N queens on an N × N chess board such that none of the queens are able to capture any other using standard chess moves for a queen. We run a numerical simulation to show that a network consisting of a combination of coupled-SQUIDs can arrive at the solution. However, conditions of the network may be trapped in incorrect answers due to the existence of local minima on the energy function of the network. The Josephson voltage oscillation effect is effective for escaping from such conditions due to the existence of local minima. We investigate network dynamics and discuss the performance of the network on the basis of the parameters of the Nb integration circuit.

Phase-mode pipelined parallel multiplier

We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices of the phase-mode logic. Experimental operations of the ICF gate and the Adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5 kA/cm/sup 2/ Nb/AlO/sub x//Nb junctions can operate over 10 GHz.

4-bit SFQ Multiplier Based on Booth Encoder

We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. The frequency of this circuit increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method.

Extended phase-mode logic-circuits with resistive ground contact

We present extended phase-mode logic (EPL) circuits which have resistive ground contact. The phase-mode logic utilizes magnetic flux-transfer and is based on pulse propagation, i.e., it is one of single flux quantum systems. The proposed logic circuits of the EPL family can have the same ground reference, contrary to the original phase-mode circuits, Therefore, it is possible to couple different EPL elements on a single ground reference. Basic components of the EPL family (a phase-conserving branch, a phase-distributing branch, and an INHIBIT gate controlled by fluxon) are presented. The phase-distributing branch and the INHIBIT gate have been fabricated using a Nb/AlO/sub x//Nb Josephson-junction technology and tested. A fan-in operation of the phase-distributing branch and the first full operation of the INHIBIT gate are successfully demonstrated. As an example of the EPL logic circuits consisting of plural gates on a single ground reference, a simulation of a 2-bit full adder circuit is also presented.<<ETX>>

Improved design for parallel multiplier based on phase-mode logic

For the improvement of the phase-mode parallel multiplier, we propose to use a Booth encoder as a substitute of an AND array. Booths algorithm is often used for the generation of partial products. The scale of the encoder does not matter for defining its operation frequency because the phase-mode Booth encoder is a pipelined structure. We suggest that the encoder is used as a serial encoder to reduce the number of Josephson junctions (JJ). There are two methods for applying the Booth encoder to the current structure. The first method is shifting multiplicands. The second method is shifting partial products and complementary signals. The total JJs in both methods are less than the AND array in large scale. The phase-mode Booth encoder with 2.5 kA/cm/sup 2/ Nb/AlO/sub x//Nb junctions can operate over 30 GHz according to the numerical simulations.

Implementation of High-Speed Single Flux-Quantum Up/Down Counter for the Neural Computation Using Stochastic Logic

We report a design and an experimental result of an SFQ up/down counter for neural computation using stochastic logic. Neural computation using stochastic logic must accumulate the pulses in order to generate the membrane potential of a neuron. A high-speed up/down counter is necessary to achieve high-speed operation. The proposed up/down counter has two operation phases which are the accumulation of signals and the access of accumulation result. Even if the number of bit increases, the operation speed of the accumulation does not decrease in this method. A 4-bit up/down counter is fabricated using niobium-trilayer standard process and successfully demonstrated. The numerical simulation shows that the up/down counter can operate up to 70 GHz with an enough bias margin in the accumulation phase.

High-speed single flux-quantum up/down counter for neural computation using stochastic logic

We propose the high-speed single flux-quantum(SFQ) up/down counter for the neural computation using stochastic logic. Up and down signals are counted by two independent counters, respectively. The proposed counter circuit can count SFQ signals of 50GHz with large operation margins. To realize the up/down counter, we fabricated a 2-bit up counter circuit and a 2-bit down counter circuit as basic blocks by Nb integrated circuits. The low-speed test results of these circuits show correct operations. We also measured dc voltages of Josephson transmission lines to investigate the responses of carry operations for SFQ pulse trains. The results show that the counter circuits have potential to count 144GHz SFQ pulses.

Design and implementation of stochastic neurosystem using SFQ logic circuits

We propose a stochastic neurosystem using SFQ logic circuits and design the main components with the following functions: carrying out the multiplication of an input to a neuron on a synaptic weight value, integrating pulses to generate a membrane potential, and generating the output of a neuron. We simulate some circuits by JSIM and confirm their correct operation. We compare two methods of multipliers: using a comparator and using a divider. The multiplication using the divider is effective with respect to integration, and reduces the accumulation time N/sub a/ required for higher precision operations. We designed a 4-bit up/down counter assuming the NEC 2.5 kA/cm/sup 2/ Nb/AlO/sub X//Nb standard process. We show that it is possible to compose the activation function circuit using a comparator.

Implementation of phase-mode arithmetic elements for parallel signal processing

We report the preliminary designs and the experimental results of high-speed digital processing elements based on phase-mode logic circuits. The core cell of these elements is a bit-serial adder cell consisting of the ICF gate which is the basic gate of phase-mode logic. Our main target is the application of the logic circuits to Digital Signal Processing. The basic arithmetic operations of DSP are a multiplication and an addition. Basic concept of the phase-mode pipelined parallel multiplier has been proposed previously. We design a 2 /spl times/ 2 AND array block and a 2-bit ripple-carry adder for the primitive parallel pipelined multiplier and also a 2-bit subtractor with a pipelined structure. These processing elements have been fabricated using NEC standard 2.5 kA/cm/sup 2/ Nb/AlOx/Nb process. The low-speed test results of these elements show correct operations. Numerical simulations show that a carry save adder (a 2-bit ripple carry adder) can operate over 10 GHz. We also discuss the prospects of large-scale SFQ DSP based on Nb junction technology.

Design and fabrication of an adder circuit in the extended phase-mode logic

We present the design and the fabrication of an adder circuit in the extended phase-mode logic family. The phase-mode logic is a single flux quantum (SFQ) logic which utilizes an SFQ as an information bit carrier. The single-bit adder circuit is made up of an INHIBIT gate which is the basic device of the phase-mode logic. The circuit has been designed and fabricated using Nb/AlO/sub x//Nb Josephson junctions with Josephson critical current density of 1.0 kA/cm/sup 2/. In order to confirm the circuit operation, the fabricated adder circuit has been tested at low speed. For investigating the possibility of a high-frequency operation, dc voltages generated by fluxon pulse trains have been measured. From the Josephson voltage-frequency relation, the result shows that the circuit has potential to complete the carry operation within 20 psec.