Koji Nakajima

Implementation of a new neurochip using stochastic logic

Even though many neurochips have been developed and investigated, the best suitable way for implementation has not been known clearly. Our approach is to exploit stochastic logic for various operations required for neural functions. The advantage of stochastic logic is that complex operations can be implemented with a few ordinary logic gates. On the other hand, the operation speed is not so fast since stochastic logic requires certain accumulation time for averaging. However, a huge integration can be achieved and its reliability is high because all of operations are done on digital circuits. Furthermore, we propose a nonmonotonic neuron realized by stochastic logic, since the nonmonotonic property is efficient for the performance enhancement in association and learning. In this paper, we show the circuit design and measurement results of a neurochip comprising 50 neurons are shown. The advantages of nonmonotonic and stochastic properties are shown clearly.

An Approach for Quantum Computing using Adiabatic Evolution Algorithm

A quantum computer employing a single quantum as a qubit executes real parallel computation and has various applications. Several algorithms have been proposed for quantum computation. However, these algorithms are applicable only to a limited number of applications. Therefore, a general purpose algorithm should be studied and developed for practical use in the near future. In this paper, we focus on the adiabatic evolution algorithm for general purpose quantum computation and discuss how to use this algorithm for solving an optimization problem. We show a new algorithm incorporating an artificial neural network (ANN)-like method in order to compose another Hamiltonian. The new algorithm is helpful for reducing computation cost and is easy to implement. Successful simulation results are shown.

Retrieval Property of Associative Memory Based on Inverse Function Delayed Neural Networks

Self-connection can enlarge the memory capacity of an associative memory based on the neural network. However, the basin size of the embedded memory state shrinks. The problem of basin size is related to undesirable stable states which are spurious. If we can destabilize these spurious states, we expect to improve the basin size. The inverse function delayed (ID) model, which includes the Bonhoeffer-van der Pol (BVP) model, has negative resistance in its dynamics. The negative resistance of the ID model can destabilize the equilibrium states on certain regions of the conventional neural network. Therefore, the associative memory based on the ID model, which has self-connection in order to enlarge the memory capacity, has the possibility to improve the basin size of the network. In this paper, we examine the fundamental characteristics of an associative memory based on the ID model by numerical simulation and show the improvement of performance compared with the conventional neural network.

Quantum adiabatic evolution algorithm for a quantum neural network

In this paper, a new quantum algorithm for solving the combinatorial optimization problems is discussed. It is based on the quantum adiabatic evolution algorithm. We propose a new method for synthesizing a Hamiltonian inspired by a Hopfield network in order to improve calculation cost. The quantum system given by a new Hamiltonian has neuron-like interactions and shows quantum behavior. We present simulation results of the new algorithm for the 4-queen problem.

Phase-mode pipelined parallel multiplier

We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices of the phase-mode logic. Experimental operations of the ICF gate and the Adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5 kA/cm/sup 2/ Nb/AlO/sub x//Nb junctions can operate over 10 GHz.

Improved design for parallel multiplier based on phase-mode logic

For the improvement of the phase-mode parallel multiplier, we propose to use a Booth encoder as a substitute of an AND array. Booths algorithm is often used for the generation of partial products. The scale of the encoder does not matter for defining its operation frequency because the phase-mode Booth encoder is a pipelined structure. We suggest that the encoder is used as a serial encoder to reduce the number of Josephson junctions (JJ). There are two methods for applying the Booth encoder to the current structure. The first method is shifting multiplicands. The second method is shifting partial products and complementary signals. The total JJs in both methods are less than the AND array in large scale. The phase-mode Booth encoder with 2.5 kA/cm/sup 2/ Nb/AlO/sub x//Nb junctions can operate over 30 GHz according to the numerical simulations.

Design and implementation of stochastic neurosystem using SFQ logic circuits

We propose a stochastic neurosystem using SFQ logic circuits and design the main components with the following functions: carrying out the multiplication of an input to a neuron on a synaptic weight value, integrating pulses to generate a membrane potential, and generating the output of a neuron. We simulate some circuits by JSIM and confirm their correct operation. We compare two methods of multipliers: using a comparator and using a divider. The multiplication using the divider is effective with respect to integration, and reduces the accumulation time N/sub a/ required for higher precision operations. We designed a 4-bit up/down counter assuming the NEC 2.5 kA/cm/sup 2/ Nb/AlO/sub X//Nb standard process. We show that it is possible to compose the activation function circuit using a comparator.

Implementation of phase-mode arithmetic elements for parallel signal processing

We report the preliminary designs and the experimental results of high-speed digital processing elements based on phase-mode logic circuits. The core cell of these elements is a bit-serial adder cell consisting of the ICF gate which is the basic gate of phase-mode logic. Our main target is the application of the logic circuits to Digital Signal Processing. The basic arithmetic operations of DSP are a multiplication and an addition. Basic concept of the phase-mode pipelined parallel multiplier has been proposed previously. We design a 2 /spl times/ 2 AND array block and a 2-bit ripple-carry adder for the primitive parallel pipelined multiplier and also a 2-bit subtractor with a pipelined structure. These processing elements have been fabricated using NEC standard 2.5 kA/cm/sup 2/ Nb/AlOx/Nb process. The low-speed test results of these elements show correct operations. Numerical simulations show that a carry save adder (a 2-bit ripple carry adder) can operate over 10 GHz. We also discuss the prospects of large-scale SFQ DSP based on Nb junction technology.

New phase-mode logic gates with large operating regions of circuit parameters

We propose new phase-mode logic gates with large operating regions of circuit perimeters. In the phase-mode logic, logic circuits are realized by combination of ICF (INHIBIT controlled by fluxon) gates. The function of the ICF gate can be achieved by the two gates which are an INHIBIT gate and an AND gate. These two gates are fabricated by NEC 2.5 kA/cm/sup 2/ Nb/AlOx/Nb standard process and successfully demonstrated. A Monte-Carlo calculation is used for evaluating yields of the gates. From 1000 calculations for each gates, we show that each yield of the INHIBIT gate and the AND gate does not decrease with increasing /spl sigma/=7% and /spl sigma/=9% which are the standard deviations of the parameter spreads. A realization of high-reliability LSI circuits will be expected by using these gates.

A new digital architecture of inverse function delayed neuron with the stochastic logic

In this paper, we present a new digital architecture of the neuron hardware that can be implemented using a field programmable gate array (FPGA). The proposed neuron applies a new inverse function delayed neuron model. In order to decrease the circuit area, we employ the stochastic logic. Because of the property of pseudoanalog operations of stochastic logic, the scale of a circuit is smaller than a conventional digital circuit. However, the stochastic logic requires the certain accumulation time for the more precise mean. Fortunately, the ID model of high-speed convergence remedies this shortcoming. The simulation experimental results show that the inverse function variance is related to the accumulation time, and this digital system can perform the associative memory.