Takeshi Yoshitome

A fast CU decision using image variance in HEVC intra coding

As the next generation standard of video coding, high efficiency video coding (HEVC) achieves high coding efficiency. The coding unit (CU) was adopted as the processing unit for HEVC to improve the coding efficiency. However, determining the optimal distribution of CU sizes requires lengthy calculation. To reduce the calculation time in intra prediction processing, we developed a method that determines the CU sizes using the variance value of the input image. Experimental results show that the proposed method reduces encoding time by about 40-70% compared to that of a conventional HEVC test model.

SuperENC: MPEG-2 video encoder chip

Thanks to increased market acceptance of applications such as digital versatile disks (DVDs), HDTV, and digital satellite broadcasting, the MPEG-2 (Moving Picture Experts Group-2) standard is becoming widely used. The MPEG-2 video standard, established in 1934, provides for a high-quality video compression format that, through high bit rates and frame rates, yields high-resolution video images. Emerging multimedia applications, such as digital versatile disk and high-definition television, demand higher quality video than ever before. In response, our MPEG-2 video encoder chip supports multiple profiles and levels.

Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level

This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. This architecture consists of triple encoding cores, a decoding core, a multiplexer/de-multiplexer core, and several dedicated application-specific hardware modules with a hierarchical flexible communication scheme for high-performance data transfer. VASA is the worlds first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multi-chip configuration. The VASA implements MPEG-2 video and system CODEC with generic audio CODEC interfaces. An LSI incorporating the architecture was successfully fabricated using the 0.13 /spl mu/m eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multi-view/-angled live TV applications with a multi-chip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.

An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture

This paper proposes a new architecture for a single-chip MPEG-2 video encoder with scalability for HDTV and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in a 0.25 /spl mu/m four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.

Development of an HDTV MPEG-2 encoder based on multiple enhanced SDTV encoding LSIs

We have developed a small, low-power HDTV MPEG-2 encoder based on a spatially parallel encoding approach. The encoder consists of multiple enhanced SDTV encoding LSIs, which have already been used to develop a single-chip, low-power MP@ML MPEG-2 video encoder.

Hierarchical analyzer for VLSI power supply networks based on a new reduction method

The author presents an algorithm for hierarchical analysis of VLSI power supply networks. The algorithms utilizes the design hierarchy and is independent of network topology. Networks in each block are recursively reduced to equivalent and small circuits in a bottom-up manner, and node voltages in the network are calculated in a top-down manner. This makes it possible to decrease the size of the matrix to be solved and to reduce the execution time. Using the prototype program XPOWER, the power lines of excess current density and voltage drop are fed back quickly to the chip floor plan designer. XPOWER reduces the matrix size to be solved from 1/10 to 1/40 and its execution is about six times faster than with the flat method for the tested examples.<<ETX>>

Scalable architecture for use in an over-HDTV real-time codec system for multiresolution video

In this paper, we propose a multi-frame synchronization method which has sufficient scalability, and describe an SHR codec system we have developed that uses MPEG-2 codecs and a multi-HDTV frame synchronizer based on our method.

Colorization matrix construction with high compression efficiency for colorization-based coding using optimization

In colorization-based coding, a chrominance component is reconstructed by applying a colorization matrix to a vector which contains a few color information. The conventional method formulated the colorization-based coding problem into an optimization problem. Since this approach obtains the optimal color information with respect to a given colorization matrix in the sense that it minimizes the reconstruction error, the compression efficiency depends on the colorization matrix. In this paper, we propose a colorization matrix construction with high compression efficiency for the colorization-based coding using optimization. To improve the ability to reconstruct the chrominance component, we construct our proposed colorization matrix based on a luminance-chrominance correlation in a local area. Furthermore, we embed an edge-preserving smoothing filtering process into the colorization matrix to reduce artifacts. The experimental results show that our method achieves better reconstruction of the chrominance component and higher compression efficiency compared with the conventional method.

Scalable architecture of real-time MP@HL MPEG-2 video encoder for multiresolution video

We have proposed a new system architecture for an MPEG-2 video encoder designed for high-resolution video. The system architecture uses the spatially parallel encoding approach and has scalability for the target video resolution to be encoded. Three new techniques have been introduced to the system. The first is a general video interface that supports multiple video formats. The second is a bitstream generation control scheme suitable for the spatially parallel encoding approach. The third is a simple data sharing mechanism for all encoding units. With these techniques, the system achieves both scalability and high encoding efficiency. Video encoding systems based on this system architecture will enable high quality video encoding to be used for visual applications for commercial and personal use at reasonable system cost.

An H.264/AVC High422 profile and MPEG-2 422 profile encoder LSI for HDTV broadcasting infrastructures

An H.264/AVC encoder LSI (named SARA/E) that supports High422 profile, as well as 422 profile of MPEG-2, has been developed for HDTV broadcasting infrastructures. It contains 257GOPS motion estimation and compensation (ME/MC) engines with search ranges of -271.75 to +199.75 (H) /-109.75 to +145.75 (V), which can utilize almost all H.264/AVC ME/MC tools, multiple reference frame, variable block size, 1/4-pel prediction, macroblock adaptive field/frame prediction, temporal/spatial direct mode, and weighted prediction. Our evaluations show that it can encode fast moving scenes with 1.2 to 1.7 dB higher than the JM. It was successfully fabricated in a 90 nm 9level metal CMOS technology. It integrates 140 million transistors.