Toshihiro Minami

Architecture and implementation of a highly parallel single-chip video DSP

The architecture of a single-chip video DSP capable of attaining a maximum performance of 300-MOPS (mega operations per second) using 0.8- mu m CMOS technology is described. The DSP is designed for the many applications regarding p*64 kb/s single-board video codecs based on DSPs that have roughly ten times the performance of conventional DSPs. Highly parallel architectures that allow four pipelined processing units to be integrated into one chip are studied extensively. The authors consider data path configurations, program sequencing control, and microinstructions that effectively support multiple pipeline processing. A prototype DSP is fabricated using 0.8- mu m CMOS technology, and some performance evaluations are presented. >

Two-chip MPEG-2 video encoder

Our two-chip, real time, MPEG-2, simple-profile-at-main-level encoder supports NTSC 4:2:0 video signals with only three external memories. We have developed a compact encoder chip set. The key features of this chip set are a low encoding delay based on a simple profile at main level; wide-range motion estimation, which it performs using a hierarchical search; a flexible, macroblock level pipeline architecture based on RISC CPUs; and three small peripherals with no glue logic: a VRAM, synchronous DRAM, and FIFO DRAM.

SuperENC: MPEG-2 video encoder chip

Thanks to increased market acceptance of applications such as digital versatile disks (DVDs), HDTV, and digital satellite broadcasting, the MPEG-2 (Moving Picture Experts Group-2) standard is becoming widely used. The MPEG-2 video standard, established in 1934, provides for a high-quality video compression format that, through high bit rates and frame rates, yields high-resolution video images. Emerging multimedia applications, such as digital versatile disk and high-definition television, demand higher quality video than ever before. In response, our MPEG-2 video encoder chip supports multiple profiles and levels.

An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture

This paper proposes a new architecture for a single-chip MPEG-2 video encoder with scalability for HDTV and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in a 0.25 /spl mu/m four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.

Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level

This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. VASA is the worlds first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multichip configuration. An LSI was successfully fabricated using the 0.13-mum eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multiview/-angled live TV applications with a multichip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.

Motion-estimation/motion-compensation hardware architecture for a scene-adaptive algorithm on a single-chip MPEG-2 MP@ML video encoder

This paper proposes a unique motion estimation and motion compensation (ME/MC) hardware architecture for a scene- adaptive algorithm. The most significant feature is the independence of the two modules for the ME/MC. This enables the encoder to analyze the statistics of a scene before encoding it and to control the whole encoding process adaptively according to the scene. The scene-adaptive controls involve changing various encoding parameters, such as the search area or selection criteria, in the slice cycle or even in the macroblock cycle. The search area of our ME/MC architecture is plus or minus 211.5 horizontally and plus or minus 113.5 vertically by the area hopping method. The architecture is loaded on a single-chip MPEG2 MPML encoder.

An Organized Firmware Verification Environment for the Programmable Image DSP

Our newly designed IDSP (Image Digita.1 Signal Processor)[1] requires a high throughput of at. least 300 NIOPS for real-time video signal processing systems (especially, for one-hoard CCITT standard p x 64 kb/s video codec ones) to enable both the parallel processing of plural pixel blocks and development in short TAT (turn-around-time). Moreover, t#he IDSP on the application systems requires soft,ware. IDSP testing, therefore, should be considered firmware testing, involving hardware and software verification. Iinpleinenting firmware test.ing, liowever, is a difficult task due to the necessity of verifying the real-time and parallel processing performance of’ the IDSP. The houiida.ry-scan tecliniciue devised by JTAG (Joint Test Action Group) is one attempt to debug a system wit11 multiprocessors.[’] 111 tliis t,echnique, a test bus controller assigns sciln paths on the system board that connects all processors’ and other devices’ scan paths and inputs and rea.ds serial data into a,nd from the a.ssigned scan path registers. However, scan path test pa,tterns, i.e., serial dat,a, have t.o he generakd for system testing. Generat,program-bus 1 programI sad-bus

A 4:2:2P@ML MPEG-2 video encoder board using an enhanced MP@ML video encoder LSI

We have developed a small, inexpensive 4:2:2P@ML encoder for consumer use by upgrading MP@ML video encoder LSI. The encoder is implemented on a PCI board and encodes video using both MP@ML and 4:2:2P@ML MPEG-2 standards.