Takeyoshi Masuda

800 V 4H-SiC RESURF-type lateral JFETs

This letter proposes to show that a lateral switching device has some unique advantages, including little dependence on substrate defects, low on-resistance, and a simple design of heat radiation. A reduced surface field (RESURF) type SiC-JFET is one of candidate devices for an electric or hybrid automobile application. Small RESURF-type SiC-JFETs with gate width of 200 /spl mu/m and a blocking voltage of 800 V were fabricated. The fabrication and characteristics of the devices are described and discussed.

A Novel Truncated V-Groove 4H-SiC MOSFET with High Avalanche Breakdown Voltage and Low Specific on-Resistance

A breakdown of a conventional trench SiC-MOSFET is caused by oxide breakdown at the bottom of the trench. We have fabricated a novel trench SiC-MOSFET with buried p+ regions and demonstrated the high breakdown voltage of 1700 V and the specific on-resistance of 3.5 mΩcm2.

Improvement of Interface State and Channel Mobility Using 4H-SiC (0-33-8) Face

In this paper, we characterized MOS devices fabricated on 4H-SiC (0-33-8) face. The interface state density of SiO2/4H-SiC(0-33-8) was significantly low compared to that of SiO2/4H-SiC(0001). The field-effect channel mobility obtained from lateral MOSFET (LMOSFET) was 80 cm2/Vs, in spite of a high p-well concentration of 5x1017 cm-3 (implantation). The double implanted MOSFET (DMOSFET) fabricated on 4H-SiC(0-33-8) showed a specific on-resistance of 4.0 mΩcm2 with a blocking voltage of 890 V.

Novel Designed SiC Devices for High Power and High Efficiency Systems

Two types of 4H-silicon carbide (SiC) MOSFETs are proposed in this paper. One is the novel designed V-groove trench MOSFET that utilizes the 4H-SiC (0-33-8) face for the channel region. The MOS interface using this face shows the extremely low interface state density (Dit) of 3 × 1011 cm2 eV-1, which causes the high channel mobility of 80 cm2 V-1 s-1 results in very low channel resistance. The buried p+ regions located close to the trench bottom can effectively alleviate the electric field crowding without the significant sacrifice of the increase of the resistance. The low specific ON-state resistance of 3.5 mQ cm2 with sufficiently high blocking voltage of 1700 V is obtained. The other is the double implanted MOSFET with the carefully designed junction termination extension and field-limiting rings for the edge termination region, and the additional doping into the junction FET region. With a high-quality and high-uniformity epitaxial layer, 6 mm × 6 mm devices are fabricated. The well balanced specific ON-state resistance of 14.2 mQ cm2 and the blocking voltage of 3850 V are obtained for 3300 V application.

Fast switching 4H-SiC V-groove trench MOSFETs with buried P + structure

4H-SiC trench MOSFETs with novel V-groove structures have been investigated. We have fabricated trench MOSFETs with the inclined 4H-SiC{0-33-8} face [1, 2] as trench sidewalls for the channel region, resulting in a low specific on-resistance owing to the superior MOS interface properties. In addition, by using buried p+ regions inside the drift layer, a high voltage avalanche breakdown without oxide break was realized as well. The specific on-resistance and breakdown voltage were 3.5 mΩ cm2 (VGS = 18 V, VDS = 1 V) and 1700 V, respectively. The switching capability of the trench MOSFET demonstrated fast dynamic characteristics without adverse effects in comparison to the trench MOSFET without buried p+ regions. Typical turn-on and turn-off time for the switching were estimated to be 92 ns and 27 ns, respectively from the resistive load switching measurements at a drain voltage of 600V.

600 V -Class V-Groove SiC MOSFETs

The authors applied a thick gate oxide layer at the trench bottoms to 600 V class truncated V-groove MOSFETs of which MOS channels were formed on 4H-SiC (0-33-8) facets and validated the static and switching characteristics. The specific on-resistance and the threshold voltage were 3.6 mΩ cm2 (VGS=18 V, VDS=1 V) and about 1 V (normally-off), respectively. The breakdown voltage of the MOSFET with a thick oxide layer was 1,125 V (IDS=1 μA). The switching losses during turn-on and turn-off operations were estimated to be 105.8 μJ and 82.5 μJ (300 V, 10 A) at room temperature. The switching characteristics exhibited low temperature dependence for turn-on/off time.

High Channel Mobility of 4H-SiC MOSFET Fabricated on Macro-Stepped Surface

Improvement of the channel mobility is needed in 4H-SiC MOSFETs for the maximum utilization of the material potential for novel power devices. We have attempted to obtain smoother MOS interfaces as one of the ways to reduce the interface states which lead to decrease of the channel mobility. We formed a terrace on the macro-stepped surface by annealing in Si melt and found that it was atomically flat. We fabricated a lateral MOSFET on the macro-stepped surface and obtained a high MOS channel mobility of 102 cm2/Vs.

The optimised design and characterization of 1200 V / 2.0 mΩ cm 2 4H-SiC V-groove trench MOSFETs

V-groove trench MOSFETs with the 4H-SiC{0-33-8} face as the trench sidewall for the channel region have been investigated. The on-resistance and breakdown voltage strongly depend on the aperture ratio of the buried p+ regions. The VMOSFETs with the buried p+ regions of 71% on a 6-inch wafer exhibited a low specific on-resistance of 2.0 mΩ cm2 with 1200 V blocking voltage. The threshold voltage is 2.3 V at 175°C, which shows the VMOSFETs have tolerability for an erroneous ignition under high temperature. The switching capability showed low switching losses over DMOSFETs on 4° off 4H-SiC(0001) face and normal operation under fast switching repetitive test (40 Vns-1). The stability of the threshold voltage was demonstrated by HTGB tests.

Low On-Resistance in 4H-SiC RESURF JFETs Fabricated with Dry Process for Implantation Metal Mask

We fabricated 4H-SiC lateral JFETs with a reduced surface field (RESURF) structure, which can prevent the concentration of electric field at the edge of the gate metal [1]. Previously, we reported on the 4H-SiC RESURF JFET with a gate length (LG) of 10 μm [2]. Its specific on-resistance was 50 mΩcm2, which was still high. Therefore, a Ti/W layer was used as an ion implantation mask so as to decrease the thickness of the mask and to improve an accuracy of the device process. A RESURF JFET with the gate length (LG) of 3.0 μm was fabricated, and the specific on-resistance of 6.3 mΩcm2 was obtained. In this paper, the fabrication process and the electrical characteristics of the device are described.

Low-Damage Indium Phosphide Sidewall Formation by Reactive Ion Etching

We investigated the sidewall damage of InP mesa structures formed by electron-cyclotron-resonance reactive ion etching (ECR-RIE) using CH4/H2. It was found that the reverse current of a p-i-n junction is affected by O2 plasma treatment used for the removal of hydrocarbon deposited during etching. The reverse current was reduced by removing the hydrocarbon, but the excessive O2 plasma treatment led to an extreme increase in the reverse current. Under optimized O2 plasma treatment conditions, the reverse current was reduced to the same level as that of the mesa formed by wet etching. Auger electron spectroscopy (AES) measurements show that phosphorus depletion and oxidization are occurred at the sidewall during the excessive O2 plasma treatment.