Toru Hiyoshi

A Novel Truncated V-Groove 4H-SiC MOSFET with High Avalanche Breakdown Voltage and Low Specific on-Resistance

A breakdown of a conventional trench SiC-MOSFET is caused by oxide breakdown at the bottom of the trench. We have fabricated a novel trench SiC-MOSFET with buried p+ regions and demonstrated the high breakdown voltage of 1700 V and the specific on-resistance of 3.5 mΩcm2.

Improvement of Interface State and Channel Mobility Using 4H-SiC (0-33-8) Face

In this paper, we characterized MOS devices fabricated on 4H-SiC (0-33-8) face. The interface state density of SiO2/4H-SiC(0-33-8) was significantly low compared to that of SiO2/4H-SiC(0001). The field-effect channel mobility obtained from lateral MOSFET (LMOSFET) was 80 cm2/Vs, in spite of a high p-well concentration of 5x1017 cm-3 (implantation). The double implanted MOSFET (DMOSFET) fabricated on 4H-SiC(0-33-8) showed a specific on-resistance of 4.0 mΩcm2 with a blocking voltage of 890 V.

Novel Designed SiC Devices for High Power and High Efficiency Systems

Two types of 4H-silicon carbide (SiC) MOSFETs are proposed in this paper. One is the novel designed V-groove trench MOSFET that utilizes the 4H-SiC (0-33-8) face for the channel region. The MOS interface using this face shows the extremely low interface state density (Dit) of 3 × 1011 cm2 eV-1, which causes the high channel mobility of 80 cm2 V-1 s-1 results in very low channel resistance. The buried p+ regions located close to the trench bottom can effectively alleviate the electric field crowding without the significant sacrifice of the increase of the resistance. The low specific ON-state resistance of 3.5 mQ cm2 with sufficiently high blocking voltage of 1700 V is obtained. The other is the double implanted MOSFET with the carefully designed junction termination extension and field-limiting rings for the edge termination region, and the additional doping into the junction FET region. With a high-quality and high-uniformity epitaxial layer, 6 mm × 6 mm devices are fabricated. The well balanced specific ON-state resistance of 14.2 mQ cm2 and the blocking voltage of 3850 V are obtained for 3300 V application.

600 V -Class V-Groove SiC MOSFETs

The authors applied a thick gate oxide layer at the trench bottoms to 600 V class truncated V-groove MOSFETs of which MOS channels were formed on 4H-SiC (0-33-8) facets and validated the static and switching characteristics. The specific on-resistance and the threshold voltage were 3.6 mΩ cm2 (VGS=18 V, VDS=1 V) and about 1 V (normally-off), respectively. The breakdown voltage of the MOSFET with a thick oxide layer was 1,125 V (IDS=1 μA). The switching losses during turn-on and turn-off operations were estimated to be 105.8 μJ and 82.5 μJ (300 V, 10 A) at room temperature. The switching characteristics exhibited low temperature dependence for turn-on/off time.

The optimised design and characterization of 1200 V / 2.0 mΩ cm 2 4H-SiC V-groove trench MOSFETs

V-groove trench MOSFETs with the 4H-SiC{0-33-8} face as the trench sidewall for the channel region have been investigated. The on-resistance and breakdown voltage strongly depend on the aperture ratio of the buried p+ regions. The VMOSFETs with the buried p+ regions of 71% on a 6-inch wafer exhibited a low specific on-resistance of 2.0 mΩ cm2 with 1200 V blocking voltage. The threshold voltage is 2.3 V at 175°C, which shows the VMOSFETs have tolerability for an erroneous ignition under high temperature. The switching capability showed low switching losses over DMOSFETs on 4° off 4H-SiC(0001) face and normal operation under fast switching repetitive test (40 Vns-1). The stability of the threshold voltage was demonstrated by HTGB tests.

Gate oxide reliability of 4H-SiC V-groove trench MOSFET under various stress conditions

The authors reported the optimization of the 4H-SiC V-groove Trench MOSFET (VMOSFET) structure in a previous conference (ISPSD2015). The VMOSFET has the buried p+ regions in the epitaxial layer to protect the trench bottom oxide. In this study, we characterized the long-term gate oxide reliability of the VMOSFETs under various stress conditions such as the gate bias or the drain bias. The VMOSFETs showed the Qbd of 28 Ccm-2 under the constant current stress TDDB measurement at RT. The threshold voltage of the VMOSFETs did not change significantly (|ΔVth|<; 0.12 V) under both the static and the switching gate bias conditions at 175°C for more than 1000 hours. The gate leakage current after the drain bias test did not change for over 6500 hours. In addition, the SCSOA of the VMOSFET was larger than 10 μsec.

The Influence of Surface Pit Shape on 4H-SiC MOSFETs Reliability under High Temperature Bias Tests

The influence of surface pit shape on 4H-SiC double implanted MOSFETs (DMOSFETs) reliability under a high temperature drain bias test has been investigated. Threading dislocations formed two types of pit shapes (deep pit and shallow pit) on an epitaxial layer surface. The cause of the failure was revealed to be an oxide breakdown above the pit generated at the threading mixed dislocation in both pit shapes. Weibull distributions between two types of pits were different. Although the DMOSFETs on the epitaxial layer with the deep pit show longer lifetime than those with the shallow pit, the epitaxial layer with the shallow pit is suitable to estimate the lifetime of the DMOSFETs because of a linearity of the Weibull plot. The lifetime of the DMOSFETs with the shallow pit was dominated by an oxide electric field. The maximum oxide electric field required to obtain the lifetime of more than 10 years was estimated to be 2.7 MV/cm.

0.97 mΩcm 2 /820 V 4H-SiC super junction V-groove trench MOSFET

We have fabricated Super Junction (SJ) V-groove trench MOSFETs (VMOSFETs), demonstrated a low specific on-resistance (RonA) of 0.97 mΩcm2 and a blocking voltage (VB) of 820 V. In the first trial, SJ structure in 4H-SiC have proved to be a good combination with MOS interface on (0-33-8) faces which keep high channel mobility in high doping concentration. We designed a protection structure called “upper p-pillar region” and demonstrated that VB lowering appeared according to its width.

Gate Oxide Reliability of 4H-SiC V-Groove Trench MOSFET with Thick Bottom Oxide

The authors reported the DMOSFETs fabricated on the 4H-SiC(0-33-8) in ECSCRM2012 and the novel V-groove MOSFETs, having (0-33-8) on the trench sidewall in ICSCRM2013. In this paper, we applied both the thick bottom oxide and the buried p+ regions to the V-groove MOSFETs for the protection of the trench bottom oxide. The V-groove MOSFET showed the low specific on-resistance of 3.2 mΩcm2 and the high blocking voltage of 1700 V on the bounty of the high channel mobility and the gate oxide protection, respectively. We also tested the gate oxide reliability of the V-groove MOSFET by constant-voltage stress TDDB measurement. The charge-to-breakdown was 18.0 C/cm2 at room temperature and 4.4 C/cm2 at 145°C. In addition, the stability of the threshold voltage was characterized with the VMOSFETs.