Takumi Okamoto

Buffered Steiner tree construction with wire sizing for interconnect layout optimization

This paper presents an efficient algorithm for buffered Steiner tree construction with wire sizing. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm finds a Steiner tree with buffer insertion and wire sizing so that the required arrival time (or timing slack) at the source is maximized. The unique contribution of our algorithm is that it performs Steiner tree construction, buffer insertion, and wire sizing simultaneously with consideration of both critical delay and total capacitance minimization by combining the performance-driven A-tree construction and dynamic programming based buffer insertion and wire sizing, while tree construction and the other delay minimization techniques were carried out independently in the past. Experimental results show the effectiveness of our approach.

A chip-stacked memory for on-chip SRAM-rich SoCs and processors

Advanced SoC chips used in multimedia devices such as mobile phones have a number of dedicated functional IP cores, including 3D graphics and video codec, and require local memories with high bit density. Each IP core is connected to closely positioned local memories for fast access and wide bandwidth. The simultaneous operation of all of IP cores on a chip is an extremely rare situation and we anticipate that future integration of more IP cores onto a chip will increase the average number of sleeping IP cores at any given time. Therefore, current chip architectures that allocate local memories to individual IP cores will become increasingly inefficient in thier use of memory resources. In contrast to this, is the use of an off-chip external memory shared by a number of IP cores.

A new feed-through assignment algorithm based on a flow model

Presents a novel feed-through assignment algorithm based on minimum-cost multi-commodity flow formulation. After finding single-commodity flow with flow conflicts on the formulation, the algorithm eliminates all the conflicts to obtain a feasible solution. Since all nets and cell rows are considered simultaneously, our algorithm globally minimizes the number of tracks, the wire length, and the number of vias. Experimental results on benchmarks show that our algorithm substantially reduces these numbers compared with conventional algorithms.

Register placement for high-performance circuits

In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthesis (CTS) for local clock optimization are used so far, but new methodologies are necessary as the technology node advances. In this paper, we study the register placement problem which is a key component of local clock optimization for highperformance circuit design along with local clock distribution. We formulate it as a minimum weighted maximum independent set problem on a weighted conflict graph and propose a novel efficient two-stage heuristic to solve it. To reduce the graph size, techniques based on register flipping and Manhattan circle are also presented. Experiments show that our heuristic can place all registers without overlaps and achieve significant improvement on the total and maximal register movement.

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations

As the feature size of VLSI circuits scales down and clock rates increases, circuit performance is becoming more sensitive to process variations. This paper proposes an algorithm of symmetrical buffer placement in symmetrical clock trees to achieve zero-skew in theory, as well as robust low skew under process or environment variations. With the completely symmetrical structure, we can eliminate many factors of clock skew such as model inaccuracy, environment temperature and intra-die process variations. We devise a new dynamic programming scheme to handle buffer placement and wire sizing under the constraint of symmetry. By classifying the wires by tree levels and defining the level-dependent blockages, the potential candidate points in the gaps of circuit blocks can be fully explored. The algorithm is efficient for minimizing source-sink delay as well as other linear cost functions. Experiments show that our method helps to obtain a balanced design of clock tree with low delay, skew and power.

Budgeting-free hierarchical design method for large scale and high-performance LSIs

This paper describes a new hierarchical design method for large scale and high-performance LSIs, which eliminates the need to perform budgeting. The budgeting step in hierarchical design partitions the total propagation time constraint for a path between any two flip-flops (FFs) in different hierarchical blocks into budgets for the different segments of the path that lie within different blocks. In practice, budgeting may result in the need for additional iterations of the synthesis and physical design flow, or may achieve sub-optimal results in terms of area, power, or clock frequency. The proposed method makes the design process budgeting-free by moving the borders of the hierarchical blocks so that all borders of the hierarchical blocks are FFs. For a commercial 500 MHz LSI with 141 million transistors, the design team required 2 months to archive the target frequency through try-and-try-again budgeting, while our budgeting-free method produced a design that meets the performance target within days