Renshen Wang

Layer minimization of escape routing in area array packaging

We devise a central triangular sequence to minimize the escape routing layers in area array packaging. We use a network flow model to analyze the bottleneck of the routable pins. The triangular patterns are generated in a reverse order from the last to the first layer. We demonstrate that the triangular pin sequence maximizes the sum of escape pins in the accumulated layers and thus minimize the number of escape routing layers. A test case is presented to illustrate the approach

3-D floorplanning using labeled tree and dual sequences

3-D packing is an NP-hard problem with wide applications in microelectronic circuit design such as 3-D packaging, 3-D VLSI placement and dynamically reconfigurable FGPA design. We present a complete representation for general non-slicing 3-D floorplan or packing structures, which uses a labeled tree and dual sequences. For each compact placement, there is a corresponding encoding. The number of possible tree-sequence combinations is (n+1)n-1(n!)2, the lowest among complete 3-D representations up to date. The construction of placement from an encoding needs O(n2) in the worst case, but in practical cases we expect O(n4⁄3 log n) time on average for circuit blocks with limited length/width ratios. Experimental results show promising performance using the labeled tree and dual sequences on 3-D floorplan and placement optimizations

Low Power Passive Equalizer Design for Computer Memory Links

Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These structures can be inserted at driver or/and receiver side at either the chip or package level and the communication bandwidth can be improved with little overhead on power consumption. Using the area of the eye as the objective function to be maximized, we optimized these equalizers for the CPU-memory interconnection of an IBM POWER6trade System with and without practical constraints on the RLCG parameter values. Our experimental results show that without employing any equalizers, the data-eye is closed for a bit-rate of 6.4 Gbps. We tried twelve different equalizer schemes and found they produce very different eye diagrams. The scheme yielding the maximum eye improves the height of the eye to more than 300 mV at a total power cost of 7.2 mW, while the scheme yielding the minimum jitter limits the jitter magnitude to 10 ps at a total power cost of 9.5 mW. We also have shown that the solution resulting from the proposed optimization approach have very small sensitivity to the tolerance of the R,L,C values and the magnitude of the coupled noise.

Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness

Interconnect dominated electronic design stimulates a demand for developing circuits on the third dimension, leading to 3-D integration. Recent advances in chip fabrication technology enable 3-D circuit manufacturing. However, there is still a possible barrier of design complexity in exploiting 3-D technologies. This article discusses the impact of migrating from 2-D to 3-D on the difficulty of floorplanning and placement. By looking at a basic formulation of the graph cuboidal dual problem, we show that the 3-D cases and the 3-layer 2.5-D cases are fundamentally more difficult than the 2-D cases in terms of computational complexity. By comparison among these cases, the intrinsic complexity in 3-D floorplan structures is revealed in the hard-to-decide relations between topological connections and geometrical contacts. The results show possible challenges in the future for physical design and CAD of 3-D integrated circuits.

Representing topological structures for 3-D floorplanning

3-D VLSI circuit is becoming a hot topic because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We review and categorize some state-of-the-art 3-D representations, and propose a twin quaternary tree (TQT) model for 3-D mosaic floorplans, extending the twin binary tree [16]. Differences between 2-D and 3-D mosaic floorplans are discussed and some 3-D properties not existing in 2-D are revealed. Though the efficiency of the twin tree for optimization heuristics is still an open question, insights from the discussions and conclusions can be helpful for 3-D physical design.

Analysis and Optimization of Low-Power Passive Equalizers for CPU–Memory Links

Several types of low-power passive equalizer are investigated and optimized in this paper. The equalizer topologies include T-junction, parallel R-C, and series R-L structures. These structures can be inserted either at the driver or the receiver side at both the chip and package level to improve the channel bandwidth of central processing unit (CPU)-memory links. Using the eye area as the objective function to be maximized, we optimize these equalizers for the CPU-memory interconnection of an IBM POWER6 system with and without practical constraints on the RLC parameter values. An efficient optimization flow combined with an algorithm predicting the worst case eye diagram is proposed and employed to optimize 42 equalizer schemes. Simulation results show that, without employing any equalizer, the data eye is closed for the bit rate of 6.4 Gb/s, while the equalized schemes can work at the bit rate of 8 Gb/s. Very promising improvements in eye height and jitter are observed with little power overhead. Simulation results also show the sensitivity of the equalization schemes to the RLC values and the effect of coupling noise.

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications

Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propose a low power design technique of gated bus which can greatly reduce power consumption on state-of-the-art bus architectures. By adding demultiplxers and adopting a novel shortest-path Steiner graph, we achieve a flexible tradeoff between large power reduction versus small wirelength increment. According to our experiments, using the gated bus we can reduce on average 93.2% of wire capacitance per transaction, nearly half of bus dynamic power and on a scale of 5%∼10% of total system power.

Noise minimization during power-up stage for a multi-domain power network

With the popularity of Multiple Power Domain (MPD) design, the multi-domain power network noise analysis and minimization is becoming important. This paper describes an efficient heuristic algorithm to arrange the power-up sequence in a multi-domain power network in order to minimize the noise. We present a formulation of this problem and show it is NP-complete. Therefore, we propose a simulated annealing (SA) based algorithm with preprocessing. Experimental results show that the proposed algorithm can minimize the noise close to the minimal values. In terms of efficiency, the SA algorithm is more than hundreds of times faster than the enumerating method and the running time scales well for these cases with the number of domains. In addition, we discuss the trade off between power-up efficiency and noise.

An improved P-admissible floorplan representation based on Corner Block List

The corner block list representation (CBL) introduced in 2000 is an efficient and effective model for floorplanning and placement while still having some limitations such as redundancy and incompleteness. In this paper, we present an auxiliary 3-route model to eliminate the redundancy and insert empty rooms to resolve the incompleteness. Finally we attain a P-admissible representation ECBL (2) which has higher performances than the original CBL and the count of its solution space is O((2n)!2/sup 6n//n!n/sup 4/).

Physical synthesis of bus matrix for high bandwidth low power on-chip communications

As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of on-chip data throughput is nowadays a critical target for SoC designers. Under this trend, bus matrices are mostly used in current system-on-chips (SoCs) because of their simplicity and good performance. We introduce a bus matrix synthesis flow to optimize on-chip communications, to keep the low delay of buses, reduce power by bus gating, and reduce wires by wire sharing. The proposed algorithms are able to help designers create high capability yet compact and efficient bus matrices for future low power SoCs.