Takumi Uezono

A device array for efficient bias-temperature instability measurements

A device array suitable for efficiently collecting statistical information on bias-temperature instability (BTI) parameters of a large number of transistors is presented. The proposed array structure substantially shortens measurement time of threshold voltage shifts under BTI conditions by parallelizing stress periods of multiple devices while maintaining 0.2mV precision. An implementation of BTI array consisting of 128 devices successfully validates stress-pipelining concept. Log-normal distributions of time exponents are experimentally observed.

On-die parameter extraction from path-delay measurements

Device-parameter estimation through path-delay measurement, which facilitates fast on-die performance prediction and diagnosis, is proposed. With the proposed technique, delays of a set of paths consisting of different logic cells are monitored. Based on the pre-characterized parameter to delay sensitivity, the process variation of a chip is estimated as an inverse problem. Discussion of desirable logic cell combination to form paths that maximize estimation accuracy is presented. Measurement of ring oscillator arrays composed of standard and customized logic cells resulted in consistent estimation of threshold voltages. Measurement accuracy is greatly enhanced by the proposed good logic cell combinations.

An Adaptive Test for Parametric Faults Based on Statistical Timing Information

The continuing miniaturization of LSI dimension is causing the increase of process-related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.

Battery-less wireless communication system through human body for in-vivo healthcare chip

This paper proposes a battery-less wireless communication system for in-vivo healthcare chip. We measured attenuation characteristics through a human body equivalent for six frequencies. Measured attenuation of 13.56 MHz is 47 dB through 15 cm thickness of human body equivalent. It is too difficult to use the usual modulations under such low power consumption. Then, we implemented the proposed system using the 13-56 MHz band with pulse interval modulation (PIM). In the simulated result, 16 mV of output voltage can be obtained at the outside receiver when coupling factor is 0.1. We also investigate antenna structure, and a tablet structure is suitable for the proposed system.

Path clustering for adaptive test

Adaptive test is one of the most efficient techniques that practically ensure high yield and reliability of designed chips. In this paper, a novel path-clustering method suitable for the adaptive test, in which test paths are altered according to the monitored process-parameters, is proposed. Considering the probability function of the die-to-die systematic process variation, the proposed method clusters path sets so that the total number of test-paths are minimized. For quantitative evaluation of different clusterings, figure of merit for clustering, which represents the expected number of test-paths at a particular test coverage, is also proposed. The proposed clustering is experimentally evaluated by applying to an industrial circuit. With our clustering, the average test paths in the adaptive test have been reduced to less than 50% compared with the ones of the conventional test.

In Vivo Batteryless Wireless Communication System for Bio-MEMS Sensors

We propose a batteryless wireless communication system for in vivo healthcare chips. The system uses inductive coupling at 13.56 MHz with internal and external coils, and employs pulse interval modulation (PIM) to endure the large attenuation in the human body. A wireless communication circuit is presented in this paper, and 16 mV of output voltage can be obtained at the external receiver. The antenna coil structure is investigated, and it is found that a tablet structure is suitable for the proposed system.

A Variability-Aware Adaptive Test Flow for Test Quality Improvement

In this paper, we propose a process-variability-aware adaptive test flow that realizes efficient and comprehensive detection of parametric faults. A parametric fault is essentially a malfunction in a large-scale integration chip, which is caused by the variability in fabrication processes. In our adaptive test framework, test pattern sets are altered on individual chips in order to apply the optimal set of test patterns for each chip, and thus the test coverage is improved and the test time is reduced. The test pattern is chosen on the basis of parameter estimations measured using an on-chip sensor with respect to statistical timing information. We also propose a novel metric to quantize the test coverage suitable for evaluating the test quality of parametric faults. Our experimental results using an industrial design show that the proposed flow significantly improves the parametric fault coverage and test efficiency compared to conventional test flows.

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation

A MOS transistor-array structure and an accurate measurement procedure of subthreshold leakage current variation is proposed. New contributions consist of two architectural improvements called LCS and PES, and measured data treatment called MCC. The LCS, leakage current cutoff switch, reduces unwanted leakage current of the non-target devices which masks the target leakage current. The PES, potential equalizing supply, further reduces masking current to an atto ampere order by setting source and drain terminals of the LCS equal. The MCC, masking current cancellation, improves measurement accuracy by subtracting remaining masking current. The proposed array structure and the procedure virtually eliminate usual constraint on the number of transistors that can be present in an array. The array structure also offers greater flexibility in choosing a row-column aspect ratio and allows different types of MOS transistors to be interweaved. Simulation study proved effectiveness of the proposed architecture showing well over a million of devices to be measurable with less than 1 % error

Via Distribution Model for Yield Estimation

In this paper, we propose a via distribution model for yield estimation. The proposed model expresses a relationship between the number of vias and wire length. We can also estimate the total number of vias in a circuit, which is derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from a gate-level netlist and layout area. We extract model parameters from the commercial chips designed for 0.18-mum and 0.13-mum CMOS processes, and demonstrate yield degradation caused by vias

RF attenuation characteristics for in vivo wireless healthcare chip

We investigate a wireless communication system for an in vivo healthcare chip. In this paper, we present measured attenuation characteristics through the human body at several frequencies. In the measurement, we use physiological saline and fresh meat instead of a real human body. From the measured results, we found that 13.56 MHz has an attenuation of 47 dB and is suitable for the proposed system.