Takuo Kikuchi

Modeling the threshold voltage instability in SiC MOSFETs at high operating temperature

The threshold voltage instability is a main reliability issue of Silicon Carbide MOS transistors submitted to gate bias stress. A new time and temperature-dependent TCAD model based on phonon-assisted tunneling is proposed. The results are compared with a previously developed temperature-independent model and with experimental data.

Modeling the threshold voltage instability in SiC MOSFETs by multiphonon-assisted tunneling

Abstract Threshold voltage instability is a main reliability issue of silicon carbide MOS transistors submitted to gate bias stress. A new time and temperature-dependent TCAD model based on multiphonon-assisted tunneling is proposed. The dynamics during both stress and recovery phase are studied and are compared with experimental data.

Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation

A novel model-based algorithm provides a capability to control full-chip design specific variation in pattern transfer caused by via/contact etch processes. This physics based algorithm is capable to detect and report etch hotspots based on the fab defined thresholds of acceptable variations in critical dimension (CD) of etched shapes for a prospective dry etch process step. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel via-contact etch (VCE) EDA tool for the design aware process optimization in addition to the ¿standard¿ process aware design optimization.