Takuya Okuyama

A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

In the near future, the ability to solve combinatorial optimization problems will be a key technique to enable the IoT era. A new computing architecture called Ising computing and implemented using CMOS circuits is proposed. This computing maps the problems to an Ising model, a model to express the behavior of magnetic spins, and solves combinatorial optimization problems efficiently exploiting its intrinsic convergence properties. In the computing, “CMOS annealing” is used to find a better solution for the problems. A 20k-spin prototype Ising chip is fabricated in 65 nm process. The Ising chip achieves 100 MHz operation and its capability of solving combinatorial optimization problems using an Ising model is confirmed. The power efficiency of the chip can be estimated to be 1800 times higher than that of a general purpose CPU when running an approximation algorithm.

24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing

In the near future, the performance growth of Neumann-architecture computers will slow down due to the end of semiconductor scaling. Presently a new computing paradigm, so-called natural computing, which maps problems to physical models and solves the problem by its own convergence property, is expected. The analog computer using superconductivity from D-Wave [1] is one of those computers. A neuron chip [2] is also one of them. We proposed a CMOS-type Ising computer [3]. The Ising computer maps problems to an Ising model, a model to express the behavior of magnetic spins (the upper left diagram in Fig. 24.3.1), and solves the problems by ground-state search operations. The energy of the system is expressed by the formula in the diagram. Computing flows are expressed in the lower flow chart in Fig. 24.3.1. In the conventional Neumann architecture, the problem is sequentially and repeatedly calculated, and therefore, the number of computing steps drastically increases as the problem size grows. In the Ising computer, in the first step, the problem is mapped to the Ising model. In the next steps, an annealing operation, the ground-state search by interactions between spins, are activated and the state transitions to the ground state where the energy of the system is minimized. The interacting operation between spins is decided by the interaction coefficients, which are set to each connection. Here, the configuration of the interaction coefficients is decided by the problem, and therefore, the interaction coefficients are equivalent to the programming in the conventional computing paradigm. The ground state corresponds to the solution of the original problem, and the solution is acquired by observing the ground state. The interactions for the annealing are performed in parallel, and the necessary steps for the annealing are smaller than that used by a sequential computing, Neumann architecture. As the table in Fig. 24.3.1, our Ising computer uses CMOS circuits to express the Ising model, and acquires the scalability and operation at room temperature.

20-GHz Focusing Antennas Based on Corrugated Waveguide Scattering

We propose a focusing antenna based on corrugated waveguide scattering at 20 GHz. Surface waves propagating on a low-loss 1-D corrugated waveguide are scattered out of the waveguide to form a focus in the free space. The scattering is caused by a chirped grating structure incorporated on the waveguide, which is designed to involve constructive interferences at a predefined focal point. In this letter, we describe the fabrication and excitation of the antenna and experimentally demonstrate focusing at 30 cm above the structure at 20 GHz. The antenna allows for beamforming of millimeter waves with a simple planar structure.

Computing architecture to perform approximated simulated annealing for Ising models

In the near future, the techniques to solve combinatorial optimization problems will become important in various fields and require large computing power. However, the performance growth of von Neumann architecture will slow down due to the end of semiconductor scaling. To resolve this problem, a computing architecture is proposed that maps the optimization problems to the ground state search of Ising models. The authors implemented the architecture, which finds the ground state by circuit operations inspired by SA, in CMOS circuits. The architecture adopts a modified algorithm using a majority function to simplify circuits. Though the power efficiency can be estimated to be 1800 times higher than that of a CPU, the modification deteriorates solution quality because it breaks the detailed balance condition. This paper presents a computing architecture that performs SA for Ising models approximately. The architecture satisfies the condition by utilizing the fact that the output of the majority voter circuit with stochastically processed inputs approximately behaves in accordance with the Glauber dynamics. Simulations demonstrate that solution quality of the proposed architecture is as good as that of SA. Our architecture can be power-efficient because the rate of increase in the number of transistors is less than 42%.

Uncertain behaviours of integrated circuits improve computational performance

Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance.

FPGA-based Annealing Processor for Ising Model

The non-von Neumann computer architecture has been widely studied towards preparing for the post-Moore era. The authors implemented the architecture, which finds the lower energy state of the Ising model using circuit operations inspired by simulated annealing, in SRAM-based integrated circuits. Our previous prototype was suited for the Ising model because of its simple and typical structure such as its three-dimensional lattice topology, but it could not be applied to real world applications. A reconfigurable prototyping environment is needed to develop the architecture, and to make it suitable for applications. Here, we describe an FPGA-based prototyping environment to develop the architecture of the annealing processor for the Ising model. We implemented the new architecture using the prototyping environment. The new architecture performs approximated simulated annealing for the Ising model, and it supports a highly complex topology. It consists of units having fully-connected multiple spins. Multiple units are placed in a two-dimensional lattice topology, and the neighboring units are connected to perform interactions between spins. The number of logic elements is reduced by sharing the operator among multiple spins within the unit. Furthermore, the pseudo-random number generator, which produces the random pulse sequences for annealing, is also shared among all the units. As a result, the number of logic elements is reduced to less than 1/10, and the solution accuracy becomes comparable to the simulated annealing running on a conventional computer.

30W wireless power transmission to networked robots through 2D waveguide

This paper examines the possibility of 30 W (more exactly 34 W) power transmission through 2D waveguide (2DW) sheet satisfying electromagnetic compatibility (EMC) requirements. The system enables wireless charging to ubiquitous robots for generating a flexible communication network. As the riskiest case in general environments, we suppose a resonant metal plate is put on a 2DW sheet. The radiated power density from any metal plates should be less than the guideline provided by International Commission on Non-Ionizing Radiation Protection (ICNIRP). Satisfying this condition, we achieve safe 30-W transmissions by thickening the surface insulator layer of 2DW to 5 cm and enlarging the coupler size to 30 by 43 cm.

An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution

We developed an SRAM-based CMOS LSI chip that accelerates ground-state searches of an Ising model. Escaping local minima is a key feature to create such a chip. We describe a novel method to escape the local minima by distributing random pulses asynchronously. The random pulses are input from outside of the chip and propagated through two asynchronous paths. In an experiment using a prototype chip, the method achieved the same solution accuracy as the conventional method. In addition, the solution accuracy was further improved by dividing the random pulse distribution path and by increasing the number of pseudo random number generators (PRNGs).