Tamara Rudenko

Mobility enhancement effect in heavily doped junctionless nanowire silicon-on-insulator metal-oxide-semiconductor field-effect transistors

The effective electron mobility in long-channel silicon-on-insulator junctionless multigate metal-oxide-semiconductor transistors is experimentally studied. It is found that the mobility in heavily doped narrow nanowire (NW) devices at low to moderately high carrier densities significantly exceeds that in wide (planar) devices with the same silicon thickness and doping and, in a certain range of carrier densities, it exceeds the mobility in bulk silicon with the same doping concentration. This effect increases when decreasing the NW width. The possible origins of this effect are discussed. These results are extremely encouraging for the development of junctionless NW transistors.

On the high-temperature subthreshold slope of thin-film SOI MOSFETs

This paper addresses the validity of the classical expression for the subthreshold swing (S) in SOI metal-oxide semiconductor field effect transistors (MOSFETs) at high temperature. Using numerical simulation, it is shown that two effects invalidate the classical expression of S at high temperature. Firstly, the depletion approximation becomes invalid and intrinsic free carriers must be taken into account to determine the effective body capacitance. Secondly, the charge-sheet model for the inversion layer becomes inaccurate due to a lowering of the electric field at the surface and a broadening of the inversion layer thickness in weak inversion. These effects must be taken into account to predict accurately the high-temperature subthreshold characteristics of both partially depleted and fully depleted SOI MOSFETs.

On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part I—Effect of Gate-Voltage-Dependent Mobility

This paper presents a study of the effect of the gate-voltage-dependent mobility on the threshold voltage extraction in long-channel MOSFETs by the transconductance change method and recently proposed transconductance-to-current ratio change method, using analytical modeling and experimental data obtained on advanced silicon-on-insulator (SOI) FinFETs and ultrathin-body SOI MOSFETs with ultrathin high- gate dielectrics. It is shown that, at vanishingly small drain voltage and constant mobility, both methods yield the same values, coinciding with the position of the maximum of the second derivative of the inversion carrier density in respect to the gate voltage. However, such is not the case anymore when considering gate-voltage dependence of mobility around threshold. Analytical expressions for the errors in the values obtained by both methods due to mobility variation around threshold are obtained. Based on analytical modeling and experimental data, it is demonstrated that, for the same mobility variation, the resulting error on the extraction caused by the gate-voltage-dependent mobility is much smaller for the transconductance-to-current ratio change method than for the transconductance change method.

On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part II—Effect of Drain Voltage

In this paper, we study the effect of the drain voltage on the threshold voltage extraction in long-channel MOSFETs by the transconductance change and transconductance-to-current ratio change methods, using analytical modeling and experimental data obtained on advanced UTB SOI MOSFETs. It is shown that, although these two methods have the same physical background, they feature radically different behaviors with respect to the drain voltage effect. In particular, the transconductance change method yields a threshold voltage value, which regularly increases with drain voltage, and interpretation, as well as analytical expression for this dependence, is provided. In contrast, for the transconductance-to-current ratio change method, the increase of the extracted threshold voltage value with drain voltage is smaller and rapidly saturates; hence, the threshold voltage extraction is more stable and reliable. Modeling derivations are found to be in excellent agreement with measurements on long-channel UTB SOI MOSFETs as well as 2-D simulations.

Border traps in 6H-SiC metal–oxide–semiconductor capacitors investigated by the thermally-stimulated current technique

We demonstrate the usefulness of the thermally-stimulated current (TSC) technique for investigating shallow interface state defects in silicon carbide metal–oxide–semiconductor (MOS) structures. For dry oxides, low-temperature TSC measurements reveal a high density of near-interfacial oxide traps (border traps) close to the band edges of 6H–SiC. Furthermore we find that annealing the SiC/SiO2 interface in pyrogenic steam at 950 °C (reoxidation) essentially reduces the density of deep interface states, while it increases the density of shallow states. Our results agree with observations of the appearance of a negative oxide charge in reoxidized MOS capacitors and the corresponding increase of the threshold voltage in n channel metal–oxide–semiconductor field-effect transistors.

Specific features of the capacitance and mobility behaviors in FinFET structures

This paper discusses experimental characterization of the gate-to-channel capacitance and the effective mobility in two types of FinFET structures: 1) with poly-Si/SiO/sub 2/ and 2) TaN/high-k dielectric gate stacks. Surprisingly, these two systems exhibit the same common features in terms of mobility and capacitance behavior of narrow-fin devices vs. quasi-planar wide-fin devices in spite of their rather different fabrication processes. Specific features revealed in effective capacitance and mobility behaviors of narrow-fin devices are discussed. We suggest that observations of the essentially lower effective dielectric capacitance and improved mobility values, in particular, the electron mobility, in narrow-fin devices compared to wide-fin devices (for both poly-Si/SiO/sub 2/ and TaN/high-k dielectric gate stacks) is related to a deeper inversion charge centroid in FinFETs operating in double-gate regime.

A revised reverse gated-diode technique for determining generation parameters in thin-film silicon-on-insulator devices and its application at high temperatures

In this paper the reverse gated-diode technique is examined for determining the carrier generation lifetime and surface generation velocities in thin-film silicon-on-insulator (SOI) devices. Using the modeling of the gate-controlled volume and surface generation components, SOI-specific aspects of the technique are highlighted. A reliable approach for extracting generation parameters in thin-film SOI devices from reverse gated-diode measurements is proposed and validated for high temperatures. The technique is demonstrated on the devices fabricated on two different SOI materials (zone-melt recrystallized and Unibond(R)), as examples of volume- and surface-dominated generation current behaviors. Finally, the technique is applied to characterize Unibond(R) SOI devices operating in the temperature range 100-300 degrees C to demonstrate the model and technique applicability at high temperatures

Electrical Properties of ZMR SOI Structures: Characterization Techniques and Experimental Results

The advantages of silicon on insulator (SOI) technology have been demonstrated in a wide range of applications, which include high-speed and radiation-tolerant CMOS devices, three-dimensional integration and very short channel VLSI circuits [1–3]. However, design and modeling of any new device require a detailed knowledge of electrical properties of used material. It is well known, that conventional characterization techniques used for bulk Si structures can not be directly applied in the case of SOI. A number of electrical characterization techniques suitable for SOI has been reported in the literature [4–6]. In this paper, characterization methods based on the use of SOI gated diode and a combined depletion-mode MOSFET and gated diode structure are presented. Proposed methods are applied to characterize both thick-and thin-film laser ZMR SOI structures.

Method for Extracting Doping Concentration and Flat-Band Voltage in Junctionless Multigate MOSFETs Using 2-D Electrostatic Effects

In this letter, we propose a new method to extract the doping concentration and flat-band voltage in junctionless (JL) multigate nanowire (NW) mosfets. The method is based on using the gate-to-channel capacitance measurements of devices with different relatively small NW widths, for which 2-D electrostatic effects are appreciable, and plotting the average carrier concentration as a function of the gate voltage. The proposed method is verified using numerical simulations and experimental data for trigate JL transistors.

Electrical properties and radiation hardness of SOI systems with multilayer buried dielectric

In this work SOI structures with buried SiO/sub 2/-Si/sub 3/N/sub 4/-SiO/sub 2/ layers have been fabricated by the ZMR-technique with the aim of improving the total dose radiation hardness of the buried dielectric layer. To optimize the fabrication process, buried layers were investigated by secondary ion mass spectrometry before and after the ZMR process, and the obtained results were compared with electrical measurements. It is shown that optimization of the preparation processes of the initial buried dielectric layers provides ZMR SOI structures with multilayer buried isolation, which are of high quality for both Si film interfaces. Particular attention is paid to the investigation of radiation-induced charge trapping in buried insulators. Buried isolation structures with a nitride layer exhibit significant reduction of radiation-induced positive charge as compared to classical buried SiO/sub 2/ layers produced by either the ZMR or the SIMOX technique.