Tamotsu Nishiyama
Panasonic
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Publication
Featured researches published by Tamotsu Nishiyama.
symposium on computer arithmetic | 1987
Shigeo Kuninobu; Tamotsu Nishiyama; Hisakazu Edamatsu; Takashi Taniguchi; Naofumi Takagi
A high speed multiplier and divider for MOS LSI based on a new algorithm is presented. When we implement the multiplier and the divider in LSI, the features such as high speed operation, small number of transistors and easy layout are the most important factors. A computational algorithm using a redundant binary representation has several excellent features such as high speed addition operations. We improved the algorithm and the method of implementation, and designed an advanced multiplier and divider with the above mentioned features. We expect mat our multiplier and divider are excellent compared with multipliers using the Booth algorithm and the Wallace tree, and with divider using the SRT method, respectively.
asian test symposium | 1994
Jiro Miyake; Gary Brown; Masahiko Ueda; Tamotsu Nishiyama
A novel method to generate test programs for functional verification of microprocessors is presented. The method combines schemes of random generation and specific sequence generation. Four levels of hierarchical information are used to generate efficient test programs including many complicated sequences. Considerations in the test generation is also discussed.<<ETX>>
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing | 1998
Jiro Miyake; Miki Urano; Genichiro Inoue; Junichi Yano; Shintaro Tsubata; Tamotsu Nishiyama; Seiji Yamaguchi
This paper describes an architecture of 23GOPS real-time video signal processor. In order to achieve high computational power and high data bandwidth for real-time video signal processing, we adopt a unique architecture based on a programmable systolic array with 90 video processing elements (VPEs). The VPE array realizes high processing ability and high flexibility by a simple structure of the VPE and a time-division multiple-operation scheme. It allows the processor to be applied to various real-time video signal processing like HD-TV (MUSE) decoding. The processor, called the digital filtering array, has been fabricated in 0.35-/spl mu/m CMOS three-metal-layer technology and achieves 23GOPS at 129.6 MHz operating frequency. Four million transistors are integrated in 13.61 mm/spl times/13.07 mm die size.
Archive | 1994
Tamotsu Nishiyama; Noriko Matsumoto
Archive | 1991
Masahiko Matsunaka; Tamotsu Nishiyama; Masahiko Ueda
Archive | 1997
Seiji Tokunoh; Noriko Matsumoto; Tamotsu Nishiyama
Archive | 1992
Tamotsu Nishiyama; Kazushi Ikeda; Tomoko Matsunaga
Archive | 1991
Noriko Matsumoto; Shoji Takaoka; Masahiko Ueda; Tamotsu Nishiyama
Archive | 2006
Tamotsu Nishiyama
Archive | 1991
Tomoko Matsunaga; Tamotsu Nishiyama