Jiro Miyake

An 8-kbit content-addressable and reentrant memory

A 256-word/spl times/32-bit associated memory, referred to as the Content Addressable and Reentrant Memory (CARM), with a 100-ns cycle time is described. The high bit density of the device is realized by a small-size associative memory cell (30/spl times/36 /spl mu/m/SUP 2/) with 2-/spl mu/m CMOS technology, while a double-layer metallization technique, new circuits for the control-signal propagation, and a hierarchical structure for the address encoder of the chip allow fast access. This device has reentrant mode operation, where the on-chip garbage collection or data storage is accomplished conditionally. One of the practical applications of this device, a high-speed matching unit for dataflow computers, is also discussed.

A 32-bit CMOS microprocessor with on-chip cache and TLB

A 32-b general-purpose microprocessor has been developed using 1-/spl mu/m CMOS technology. The chip, containing 372 K transistors, operates at a 80-ns machine cycle time with a 5-V power supply. For virtual and hierarchical memory system support, a 64-entry full-associative translation lookaside buffer (TLB) and a 2-kbyte instruction cache are implemented on the chip. The internal access times for the TLB and cache are 22 and 18 ns, respectively. The microarchitecture has been designed to reduce the pipeline to three stages, simplifying the control path and obtaining high-speed performance. The data path of this chip is also enhanced with hardware, such as a barrel shifter and multiplier/divider. The chip performance has been measured to be 5.1 million instructions per second (MIPS) and 50-ns-access main memory.

Automatic test generation for functional verification of microprocessors

A novel method to generate test programs for functional verification of microprocessors is presented. The method combines schemes of random generation and specific sequence generation. Four levels of hierarchical information are used to generate efficient test programs including many complicated sequences. Considerations in the test generation is also discussed.<<ETX>>

A CMOS 32b microprocessor with on-chip cache and transmission lookahead buffer

THIS PAPER WILL DESCRIBE a singlechip CMOS 32b microprocessor supporting a smart memory hierarchy with on-chip Cache and TLB (Transmission Lookaside Buffer). The chip, containing 372k transistors, has been fabricated by using a double-metal layer CMOS technology with lpn design rule. It operates at 8011s machine cycle time and dissipates 1.7W. A high-speed address translation device is essential for the virtual memory system, and two full-associative TLBs for supervisor and user mode, respectively, are implemented for that purpose. Each device has 32 entries composed of a 28b data field (SRAM), a 29b tag field (CAM’) and replace control LRU (Least-Recently-Used) circuits: Figure 1. The pageoize can be varied from 512 to 4K bytes by 3b searchmasking of virtual address tag bits. The TLB access time is less than 22ns, with a half machine cycle (40ns) for a complete address translation, virtua2 to phys ica l , and carried out by an off-chip TLB in about 100ns. The replacement algorithm, LRU, is realized by a 32 x 5b matrix of magnitude comparator and counter. The tag field includes task-ID (TID) bits, in addition to virtual address bits and a valid bit. The task-ID bits are used for checking and taskassigned invalidation of entries. These functions serve for effective management and rapid context switching in a multi-tasking system. The LKbyte Instruction Cache relieves a I/O bottle-neck. A lpm-process technology permits the cache to be of large enough size for the multi-task environment. Its structure is two-way set associative, and 256 x 2 entries are composed of 26b tag fields (SRAM) and 32h data fields (SRAM): Figure 2. This Cache is virtually addressed, and its access time is less than 18ns in the hit case.

A 40 MIPS (peak) 64-bit microprocessor with one-clock physical cache load/store

A 64-b RISC (reduced-instruction-set-computer) microprocessor that performs a load/store instruction in one clock and achieves 40 MIPS and 20-MFLOPS peak performance at 40 MHz clock is described. Two techniques are used to attain this performance: (1) two translation lookaside buffers (TLBs) with parallel and hierarchical word-line transition detection circuits; (2) a self-clocked register file using a data-flow clocking scheme. A floating-point unit performs single- and double-precision floating-point operations concurrently with an integer unit. The chip is fabricated using 0.8- mu m double-metal CMOS technology. About 1M transistors are contained in the 14.85*15. 13-mm die housed in a 238-pin pin-grid array (PGA).<<ETX>>

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

A 1-million transistor 64-b microprocessor has been fabricated using 0.8- mu m double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit. >

Architecture of 23GOPS video signal processor with programmable systolic array

This paper describes an architecture of 23GOPS real-time video signal processor. In order to achieve high computational power and high data bandwidth for real-time video signal processing, we adopt a unique architecture based on a programmable systolic array with 90 video processing elements (VPEs). The VPE array realizes high processing ability and high flexibility by a simple structure of the VPE and a time-division multiple-operation scheme. It allows the processor to be applied to various real-time video signal processing like HD-TV (MUSE) decoding. The processor, called the digital filtering array, has been fabricated in 0.35-/spl mu/m CMOS three-metal-layer technology and achieves 23GOPS at 129.6 MHz operating frequency. Four million transistors are integrated in 13.61 mm/spl times/13.07 mm die size.

23 GOPS programmable systolic array DSP for video signal processing

A 23GOPS programmable systolic array DSP for real-time video signal processing, called digital filtering array (DFA), is described. The DFA performs at the 129.6MHz clock rate with its 90 video processing element (VPE) array. HDTV (MUSE) signal decoding can be realized with 3 DFA chips. The DFA also can be used in other video signal processing applications because ofits programmability.