Tapani Ahonen

Applying CDMA Technique to Network-on-Chip

The issues of applying the code-division multiple access (CDMA) technique to an on-chip packet switched communication network are discussed in this paper. A packet switched network-on-chip (NoC) that applies the CDMA technique is realized in register-transfer level (RTL) using VHDL. The realized CDMA NoC supports the globally-asynchronous locally-synchronous (GALS) communication scheme by applying both synchronous and asynchronous designs. In a packet switched NoC, which applies a point-to-point connection scheme, e.g., a ring topology NoC, data transfer latency varies largely if the packets are transferred to different destinations or to the same destination through different routes in the network. The CDMA NoC can eliminate the data transfer latency variations by sharing the data communication media among multiple users concurrently. A six-node GALS CDMA on-chip network is modeled and simulated. The characteristics of the CDMA NoC are examined by comparing them with the characteristics of an on-chip bidirectional ring topology network. The simulation results reveal that the data transfer latency in the CDMA NoC is a constant value for a certain length of packet and is equivalent to the best case data transfer latency in the bidirectional ring network when data path width is set to 32 bits.

Topology optimization for application-specific networks-on-chip

Compared to the well understood macro networks, networks-on-chip introduce novel design challenges. The characteristics of the system data flows and the knowledge of the required wire lengths can be exploited to optimize for speed and power consumption. A component library for flexible construction of interconnection architectures is being developed at the Tampere University of Technology to enable the creation of application development platforms. The overall design flow of these development platforms is reviewed in this paper. Network-on-chip topology optimization is addressed by describing the methodologies used by an effective design automation tool. The detailed cost functions of the tool capture the factors contributing to the speed and power consumption of asynchronous interconnections, while different abstraction level input information is supported. A case study into the application domain of industrial process control and monitoring is presented in order to evaluate the result quality.

Issues in the development of a practical NoC: the Proteo concept

Network-on-Chip will be one of the cornerstones of future electronics. At Tampere University of Technology we have been working on the development of our own proposal for a flexible on-chip communication network, called Proteo. Proteo introduces the concept of an open library of communication components that can be selected and configured to build highly-customized networks-on-chip. The designer of a new System-on-Chip platform starts with a description of the hardware components of the system and an abstract model of the problem application, and with the help of the Proteo software tools, obtains a synthesizable instance of a packet-switching network that, ideally, meets his requirements. The constraints placed on the type of designs that may use Proteo are minimal and an important part of the process should be automated. In this article we introduce the philosophy behind the project in relation to fundamental deep submicron technology problems, and some of our initial results.

Multicore software-defined radio architecture for GNSS receiver signal processing

We describe a multicore Software-Defined Radio (SDR) architecture for Global Navigation Satellite System (GNSS) receiver implementation. A GNSS receiver picks up very low power signals from multiple satellites and then uses dedicated processing to demodulate and measure the exact timing of these signals from which the users position, velocity, and time (PVT) can be estimated. Three GNSS SDR architectures are discussed. (1) A hardware-based SDR that is feasible for embedded devices but relatively expensive, (2) a pure SDR approach that has high level of flexibility and low bill of material, but is not yet suited for handheld applications, and (3) a novel architecture that uses a programmable array of multiple processing cores that exhibits both flexibility and potential for mobile devices. We present the CRISP project where the multicore architecture will be realized along with numerical analysis of application requirements of the platforms processing cores and network payload.

State of the art baseband DSP platforms for Software Defined Radio: A survey

Software Defined Radio (SDR) is an innovative approach which is becoming a more and more promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities and industries to support SDR applications. This article presents an overview of current platforms and analyzes the related architectural choices, the current issues in SDR, as well as potential future trends.

Hierarchically Heterogeneous Network-on-Chip

We observed several inefficiencies arising from the utilization of a global network to interconnect local bus clusters in our previous work. The observations were made with applications running on an FPGA prototype of a multimedia processing platform. The presented network-on-chip concept has been designed to eliminate these inefficiencies. This hierarchically heterogeneous architecture provides increased bandwidth inside processing clusters by local switches that replace shared buses. Features include priority-based low-latency arbitration logic with a memory space conserving programming model. Run-time reconfigurable source routing generates output port selects for the traversed path. The realization was carefully designed for easy and efficient implementation on any technology. Arbitrated 5 times 5 mesh switch implementations on an ASIC technology feature as few as two thousand gates and only five levels of logic on the critical path.

CRISP: Cutting Edge Reconfigurable ICs for Stream Processing

The Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project aims to create a highly scalable and dependable reconfigurable system concept for a wide range of tomorrow’s streaming DSP applications. Within CRISP, a network-on-chip based many-core stream processor with dependability infrastructure and run-time resource management is devised, implemented, and manufactured to demonstrate a coarse-grained core-level reconfigurable system with scalable computing power, flexibility, and dependability. This chapter introduces CRISP, presents the concepts, and outlines the preliminary results of a running project.

Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems

Designing accelerators for the real-time computation of Fast Fourier Transform (FFT) algorithms for state-of-the-art Orthogonal Frequency-Division Multiplexing (OFDM) demodulators has always been challenging. We have scaled-up a template-based Coarse-Grain Reconfigurable Array device for faster FFT processing that generates special purpose accelerators based on the user input. Using a basic and a scaled-up version, we have generated a radix-4 and mixed-radix (2, 4) FFT accelerator to process different length and types of algorithms. Our implementation results show that these accelerators satisfy not only the execution time requirements of FFT processing for Single Input Single Output (SISO) wireless standards that are IEEE-802.11 a/g and 3GPP-LTE but also for Multiple Input Multiple Output (MIMO) IEEE-802.11n standard.

A synthesizable RTL design of asynchronous FIFO

An asynchronous FIFO which avoids data movement in a micropipeline FIFO is presented and it has been implemented as a gate-level netlist. The presented asynchronous FIFO model is constructed by commonly used hardware-description language and synthesized using the conventional EDA tools and methods for synchronous design. The purpose of this work is to construct a reusable asynchronous FIFO design which suits the commonly used synchronous design tools and flow.

Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools

An FPGA prototype of a four-node globally-asynchronous locally-synchronous network-on-chip is described. The network for global communication operates asynchronously at the link level and synchronously within a node. Two C-element control pipelines constitute the control logic for the asynchronous part. C-element and asynchronous arbiter realizations on FPGA using standard synchronous design tools are presented