Tero Nurmi

Interconnection of autonomous error-tolerant cells

In this paper we propose an interconnection scheme for the autonomous error-tolerant (AET) cell introduced in a paper by Valtonen et al. (2001). The objective here is to partition the system into identical, physically autonomous and highly configurable cells that can operate without outside control or synchronization. In billion transistor Network-on-Chip (NoC) circuits, an AET cell fabric could prove highly flexible and reliable, and allow for low replication costs, due to homogeneousity. However, many challenges persist before a useful system can be constructed: the need for (i) scalable long-distance communication-global bus wiring fits poorly into a homogeneous, symmetric fabric and limits scalability, (ii) flexible communication-cells in all directions, within a given range, should be accessible and (iii) self-synchronizing topologies, due to the absence of external synchronization; (iv) the interconnect scheme is to be implemented using near-future technology generations, and (v) the fabric should be efficient when constituting billions of cells.

Block-wise extraction of Rent's exponents for an extensible processor

It is envisioned that future system-on-chip hardware platform designs will be based on reuse of a customizable processor core. Consequently, being able to quickly evaluate the key performance metrics associated with specific points in the design space becomes essential. Development of an early design phase performance estimation method for logic blocks of an extensible processor core is described. The processor blocks were systematically synthesized with varying constraints for reference and the corresponding Rents exponents were extracted from the results. The impact of synthesis-originated design space discontinuities on the accuracy of physical performance estimation was evaluated by applying linear regression on the resulting design points.

A system-level framework for designing and evaluating protocol processor architectures

To meet the tightening requirements on network hardware, the design of programmable processors with network-optimised hardware, that is, network or protocol processors, has attracted interest. In this paper, we address evaluation of different architectural configurations for such processors, and reuse of previously designed components in later design projects. The proposed system-level framework enables easy and fast experimentation with different protocol processor hardware architecture configurations to estimate their performance characteristics at early stages in the design process. We conclude the paper with examples of designing processors using the framework.

A Brunch from the Coffee Table-Case Study in NoC Platform Design

Tapani Ahonen*, Seppo Virtanen**, Juha Kylliäinen*, Dragos Truscan***, Tuukka Kasanko*, David Sigüenza-Tortosa*, Tapio Ristimäki*, Jani Paakkulainen**, Tero Nurmi**, Ilkka Saastamoinen*, Hannu Isännäinen*, Johan Lilius***, Jari Nurmi*, and Jouni Isoaho** *Institute of Digital and Computer Systems, Tampere University of Technology, Finland **Department of Information Technology, University of Turku, Finland ***Department of Computer Science, Åbo Akademi University, Finland

New course on computational platforms towards nanoscale systems

In this paper we present an educational approach for a paradigm shift needed when changing from deep submicron CMOS designs to real nano and nanoscale technologies (Waser, 2005) in complex communication and computation system implementations. Here we present an introduction course implemented for starting the paradigm shift in curriculum. Here we present course targets, structure and implementation as well as future designer competence profiles. The course is consisting of five thematic areas: nanoscale technologies, parallel platforms, concurrent algorithms, reconfigurable systems and autonomous system management. These thematic areas compound the core of future nanosystems educational program upgrades for current NoC curricula.

Capturing processor architectures from protocol processing applications: a case study

We present a case study in finding optimized processor architectures for a given protocol processing application. The process involves application analysis, hardware/software partitioning and optimization, and evaluation of design quality through simulations, estimations and synthesis. The case study was targeted at processing key IPv6 routing functions at 200 MHz using 0.18 /spl mu/m CMOS technology. A comparison to an implementation on a commercial processor revealed that the captured architectures provided similar or better performance. Especially checksum calculation was efficient in the captured architectures.

Global Interconnect Analysis

In this chapter we studied principles for system-level interconnect modeling. The main focus was to examine global wires that distribute signals between di erent system blocks. Additionally, power distribution was dealt with in the end of the chapter by using the maximum allowed power supply voltage variation as a constraint to design power distribution network in a proper way. We examined electrical properties of on-chip wires and discussed shortly some possible interconnect schemes in SoC and NoC. Some interconnect schemes in SoC and NoC were shortly discussed. We used Rent’s rule and multiple Rent’s exponents to evaluate cost functions that di erent system blocks set for the global wiring (both signal and power distribution). We optimized our signaling to achieve the maximum bandwidth, the minimum delay by using properly sized and placed repeaters and finally presented a joint optimization case study in which both power distribution and signal distribution in global wires were simultaneously optimized. Our analysis revealed that both early cost/performance estimation of resources (i.e. functional blocks) and the joint optimization of global signal and power estimation are essential when designing future SoCs and NoCs.