Tarek Zaki

Contact Resistance and Megahertz Operation of Aggressively Scaled Organic Transistors

Bottom-gate, top-contact organic thin-film transistors (TFTs) with excellent static characteristics (on/off ratio: 10(7) ; intrinsic mobility: 3 cm(2) (V s)(-1) ) and fast unipolar ring oscillators (signal delay as short as 230 ns per stage) are fabricated. The significant contribution of the transfer length to the relation between channel length, contact length, contact resistance, effective mobility, and cutoff frequency of the TFTs is theoretically and experimentally analyzed.

Flexible Low‐Voltage Organic Complementary Circuits: Finding the Optimum Combination of Semiconductors and Monolayer Gate Dielectrics

Low-voltage p-channel and n-channel organic transistors with channel lengths down to 0.5 μm using four small-molecule semiconductors and ultra-thin dielectrics based on two different phosphonic acid monolayers are fabricated on plastic substrates and studied in terms of effective mobility, intrinsic mobility and contact resistance. For the optimum materials combination, flexible complementary circuits have signal delays of 3.1 μs at 5 V.

A 3.3 V 6-Bit 100 kS/s Current-Steering Digital-to-Analog Converter Using Organic P-Type Thin-Film Transistors on Glass

A 3.3 V 6-bit binary-weighted current-steering digital-to-converter converter (DAC) using low-voltage organic p-type thin-film transistors (OTFTs) is presented. The converter marks records in speed and compactness owing to an OTFT fabrication process that is based on high-resolution silicon stencil masks. The chip has been fabricated on a glass substrate and consumes an area of 2.6× 4.6 mm2. The converter has a maximum update rate of 100 kS/s and a maximum output voltage swing of 2 V. The measured DNL and INL at an update rate of 1 kS/s are - 0.69 and 1.16 LSB, respectively. A spurious-free dynamic range (SFDR) of 32 dB has been measured for output sinusoids at 31 Hz (update rate of 1 kS/s) and 3.1 kHz (update rate of 100 kS/s).

Contact properties of high-mobility, air-stable, low-voltage organic n-channel thin-film transistors based on a naphthalene tetracarboxylic diimide

Air-stable bottom-gate, top-contact n-channel organic transistors based on a naphthalene diimide exhibiting electron mobilities up to 0.8 cm2/Vs at low voltages were fabricated. Transistors with channel lengths of 1 μm show a transconductance of 60 mS/m, but are significantly limited by the contact resistance. Transmission line measurements in combination with contact resistance models were applied to investigate this influence. Both contact resistance and contact resistivity are proportional to the inverse gate overdrive voltage. Organic complementary ring oscillators were fabricated on a flexible plastic substrate showing record signal delays down to 17 μs at a supply voltage of 2.6 V.

S-Parameter Characterization of Submicrometer Low-Voltage Organic Thin-Film Transistors

This letter presents the first comprehensive experimental studies on the frequency response of staggered low-voltage organic thin-film transistors (OTFTs) using S-parameter measurements. The transistors utilize air-stable dinaphtho-thieno-thiophene as the organic semiconductor with various channel lengths and gate overlaps. A peak cutoff frequency of 3.7 MHz for a channel length of 0.6 μm, gate overlap of 5 μm, and a supply voltage of 3 V is achieved. In view of the low supply voltage and air-stability, this result marks a record achievement in OTFT technology. The channel length dependence of the cutoff frequency is described in a compact model and a close correspondence to the measured data of OTFTs with variable device dimensions is shown. Moreover, the cutoff frequencies at different gate biases are found to be proportional to the dc transconductance.

Accurate Capacitance Modeling and Characterization of Organic Thin-Film Transistors

This paper presents analysis of the charge storage behavior in organic thin-film transistors (OTFTs) by means of admittance characterization, compact modeling, and 2-D device simulation. The measurements are performed for frequencies ranging from 100 Hz to 1 MHz and bias potentials from zero to -3 V on top-contact OTFTs that employ air-stable and high-mobility dinaphtho-thieno-thiophene as the organic semiconductor. It is demonstrated that the dependence of the intrinsic OTFT gate-source and gate-drain capacitances on the applied voltages agrees very well with Meyers capacitance model. Furthermore, the impact of parasitic elements, including fringe current and contact impedance, is investigated. The parameters used for the simulation and modeling of all the dynamic characteristics correspond closely to those extracted from static measurements. Finally, the implications of the admittance measurements are also discussed relating to the OTFTs dynamic performance, particularly the cutoff frequency and the charge response time.

A 3.3V 6b 100kS/s current-steering D/A converter using organic thin-film transistors on glass

Organic thin-film transistors (OTFT) processed at low-temperatures offer prospects for a vast number of integrated circuit applications in mechanically flexible, inexpensive, large-area and biomedical electronics [1]. In addition, the low-voltage operation capability of recent OTFTs makes them well-suited for battery-powered or radio frequency-coupled portable devices [2]. In such applications, data conversion to interface the digital processors with the analog world is an essential necessity. Here, we demonstrate a compact 6b current-steering D/A converter (DAC) circuit, built in OTFT technology, which is 1000× faster and 30× smaller than the previously published data for a 6b DAC [3]. These considerable improvements result from an OTFT fabrication process based on silicon stencil masks that provide submicron channel length capability and excellent transistor matching [4], [5].

Si stencil masks for organic thin film transistor fabrication

Organic electronics are gaining increasing interest and attention in electronic device fabrication due to cost advantages and low process manufacturing temperatures, which allow the use of mechanically-flexible polymeric substrates. Different patterning techniques for Organic Thin Film Transistors (OTFT) with sub μm channel length are currently under investigation like inkjet-printing, nanoimprint, optical- and e-beam lithography. This paper describes a new approach for OTFT fabrication by device patterning with Si stencil lithography. This high resolution shadow mask technique allows the parallel patterning of sub μm features without the use of photosensitive resists or chemical solvents, which could lead to a degradation of the sensitive organic semiconductor layer. At first the device pattern is etched into a thin Si membrane layer, creating design-specific sub μm features. Subsequent this stencil mask is aligned and clamped to the substrate and material is deposited through the stencil apertures forming the desired device pattern onto the substrate. By repeating this sequence with different deposition materials a classical top contact TFT architecture with a gate electrode, gate dielectric, organic semiconductor and source drain contacts can be achieved.

Circuit impact of device and interconnect parasitics in a complementary low-voltage organic thin-film technology

A simulation case study to indicate advancement opportunities for a low-voltage complementary organic thin-film transistor (OTFT) technology is presented. A 3-bit unary current-steering digital-to-analog converter (DAC) is used as circuit test vehicle. The study is based on accurate agreement of simulated and measured data, owing to optimized DC/AC SPICE models for both p- and n-type OTFTs. The model is validated by transient measurements of the driving complementary logic thermometer decoder up to a maximum operating frequency of 1 kHz. The case study shows that an improved circuit performance will result from a smaller source and drain overlap with the gate electrode particularly in the n-type OTFT, from avoiding metal interconnect crossings, and from increasing the channel carrier mobility of the n-type OTFT.

Design of a quadrature clock conditioning circuit in 90-nm CMOS technology

This paper presents the operation and problems of the conventional clock conditioning circuits. A modified design is proposed to eliminate these problems and to merge two conditioning circuits together. This is to adjust and maintain two output signal properties actively during circuit operation for 4-phase 10 GHz single-ended clock signals. It is desired to have an exact 50% duty-cycle for each signal and a 90° phase difference between them. Simulation results in 90-nm CMOS technology are provided showing low output jitter.