Tarun Kanti Bhattacharyya

Microelectromechanical resonators for radio frequency communication applications

Over the past few years, microelectromechanical system (MEMS) based on-chip resonators have shown significant potential for sensing and high frequency signal processing applications. This is due to their excellent features like small size, large frequency-quality factor product, low power consumption, low cost batch fabrication, and integrability with CMOS IC technology. Radio frequency communication circuits like reference oscillators, filters, and mixers based on such MEMS resonators can be utilized for meeting the increasing count of RF components likely to be demanded by the next generation multi-band/multi-mode wireless devices. MEMS resonators can provide a feasible alternative to the present-day well-established quartz crystal technology that is riddled with major drawbacks like relatively large size, high cost, and low compatibility with IC chips. This article presents a survey of the developments in this field of resonant MEMS structures with detailed enumeration on the various micromechanical resonator types, modes of vibration, equivalent mechanical and electrical models, materials and technologies used for fabrication, and the application of the resonators for implementing oscillators and filters. These are followed by a discussion on the challenges for RF MEMS technology in comparison to quartz crystal technology; like high precision, stability, reliability, need for hermetic packaging etc., which remain to be addressed for enabling the inclusion of micromechanical resonators into tomorrow’s highly integrated communication systems.

Position Mutated Hierarchical Particle Swarm Optimization and its Application in Synthesis of Unequally Spaced Antenna Arrays

A family of position mutated hierarchical particle swarm optimization algorithms with time varying acceleration coefficients (viz. PM_nHPSO-TVAC, n = 1, 2, 3, 4) is introduced in this paper. The proposed position mutation schemes help the swarm to get out of local optima traps and the hierarchical nature of the swarm prevents premature convergence. One distinct advantage of the proposed algorithms over the existing mutated PSO algorithms is that PM_nHPSO-TVAC do not involve any controlling parameter. Performance of the proposed algorithms is evaluated on standard benchmark functions. Comparative study shows that PM_4HPSO-TVAC performs better than the other PM_n HPSO-TVAC, HPSO-TVAC, comprehensive learning PSO (CLPSO), adaptive-CLPSO (A-CLSPO), PSO with time-varying inertia weight (PSO-TVIW), and constriction factor PSO (CFPSO) for the benchmark functions considered. We apply the proposed algorithm to the synthesis of uniformly excited, unequally dpaced linear array to minimize sidelobe level (SLL) and to control first-null-beamwidth (FNBW) and null locations. Further, we apply the proposed algorithm to the synthesis of unequally spaced sparse planar array to minimize SLL.

Characterization of diamond-like nanocomposite thin films grown by plasma enhanced chemical vapor deposition

Diamond-like nanocomposite (DLN) thin films, comprising the networks of a-C:H and a-Si:O were deposited on pyrex glass or silicon substrate using gas precursors (e.g., hexamethyldisilane, hexamethyldisiloxane, hexamethyldisilazane, or their different combinations) mixed with argon gas, by plasma enhanced chemical vapor deposition technique. Surface morphology of DLN films was analyzed by atomic force microscopy. High-resolution transmission electron microscopic result shows that the films contain nanoparticles within the amorphous structure. Fourier transform infrared spectroscopy (FTIR), Raman spectroscopy, and x-ray photoelectron spectroscopy (XPS) were used to determine the structural change within the DLN films. The hardness and friction coefficient of the films were measured by nanoindentation and scratch test techniques, respectively. FTIR and XPS studies show the presence of CC, CH, SiC, and SiH bonds in the a-C:H and a-Si:O networks. Using Raman spectroscopy, we also found that the hardness of...

Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design

The paper reports the implementation of a frequency synthesizer for system-on-chip (SOC) design. The epi-digital CMOS process is used to provide SOC solution. This work focuses on low-power consumption to achieve longer life-time of batteries. A 2.4GHz frequency synthesizer has been fabricated in 0.18µm epi-digital CMOS technology for ZigBee applications, which consumed 7.95 mW from 1.8V supply. The synthesizer has achieved phase-noise of −81.55dBc/Hz and −108. 55dBc/Hz at 100kHz and 1MHz offset, respectively. The settling time measured is less than 25µs for an output frequency change of 75MHz from 2.4GHz. The chip core area is 0.75 × 0.65mm2.

Humidity Sensor Based on High Proton Conductivity of Graphene Oxide

This paper explores the performance of graphene oxide (GO) as humidity sensor. GO was synthesized using modified Hummers and Offeman method, and the sensing layer was characterized using optical microscope, scanning electron microscopy, atomic force microscopy, transmission electron microscopy, and X-ray photoelectron spectroscopy. The sensor devices were fabricated by drop-casting of GO on patterned gold electrodes on Si/SiO2 substrate. GO-based sensor was exposed to six different relative humidity (RH%), and the response of our sensor was found to be excellent due to large proton conduction. The sensor response varied from ~180 times (40% RH) to ~1200 times (88% RH). Our GO-based humidity sensor also showed ultrafast response and recovery times with extremely good repeatability. Also, the role of functional groups in humidity sensing was explored by fabricating the sensor devices by thermally reducing GO for different time durations. We believe GO could potentially be used to develop new-generation ultrasensitive humidity sensor.

Deoxyribonucleic Acid Functionalized Carbon Nanotube Network as Humidity Sensors

In this paper, deoxyribonucleic acid functionalized carbon nanotube (DFC) network has been used to develop field effect transistor (FET)-based humidity sensor. The sensor works on the principle of variation of conductance of the DFC network with change in relative humidity. Since the output signal current of the sensor increases exponentially with increase in RH, the device offers higher sensitivity especially at higher RH. The response and recovery times of this zero gate biased FET-based humidity sensor are measured to be 4 and 8 s, respectively, and offers no baseline shift during recovery, which indicates that the sensing mechanism is governed by charge transfer between the DFC and water molecules. The device is highly selective to atmospheric humidity, having no response to nitrogen and oxygen. The effect of temperature on the performance of the sensor is also studied and reported in this paper.

A high o/p resistance, wide swing and perfect current matching charge pump having switching circuit for PLL

The charge pump (CP) circuit is one of the main building block in a phase-locked loop (PLL) based frequency synthesizers. In conventional CMOS charge pump circuits, there are some non-ideal effects such as clock feed through, current mismatch and charge sharing which result in a phase offset in phase-locked loop circuits. This paper presents a new charge pump circuit in 0.18@mm CMOS technology, which greatly reduces the mismatch of current between two branches of the cascode current mirror. By using this proposed architecture, the mismatching between the UP/DN current of the CP can be achieved with less than 0.065% from post-layout simulation. As a result the spur and also the overall phase noise of the PLL are reduced. The charge pump output voltage range is 0.40-1.25V. Additionally, the proposed circuit has wide output voltage swing and high output resistance, which ensures its good performance under very low power supply. Further, this CP circuit is incorporated with a new switching circuit to eliminate the clock feed through and charge injection error.

Fully integrated CMOS frequency synthesizer for ZigBee applications

A single chip frequency synthesizer compliant with the ZigBee standard is designed in a standard 0.18/spl mu/ CMOS process. Integer N topology is chosen for the implementation. Synthesizer consists of third order passive loop filter; a CML based programmable frequency divider, a standard tristate PFD, a switch on source topology based charge pump and an on chip quadrature VCO. Simulated settling time is 300/spl mu/sec. Synthesizer consumes 22mW of power at supply voltage of 1.8 V and occupies an active area of mm/sup 2/.

The evolution of graphene-based electronic devices

Successful isolation of single-layer graphene, the two-dimensional allotrope of carbon from graphite, has fuelled a lot of interest in exploring the feasibility of using it for fabrication of various electronic devices, particularly because of its exceptional electronic properties. Graphene is poised to save Moores law by acting as a successor of silicon-based electronics. This article reviews the success story of this allotrope with a focus on the structure, properties and preparation of graphene as well as its various device applications.

7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency Synthesizer

A fully-integrated, ZigBee standard compliant, frequency synthesizer in the frequency range of 2.4-2.4835 GHz with frequency resolution of 5MHz, is designed in 0.18mum epi-CMOS process and silicon performance is measured. Integer-N architecture is chosen for implementation. It consumes 7.95mW of power at 1.8V supply and core area is 0.75times0.65mm2. The measured phase-noises are -81.55dBc/Hz and -108.55dBc/Hz at 100kHz and 1MHz offset, respectively, with low settling time less than 25mus