Ashudeb Dutta

Fully Concurrent Dual-Band LNA Operating in 900 MHz/2.4 GHz Bands for Multi-standard Wireless Receiver with Sub-2dB Noise Figure

This article presents the design of a fully concurrent dual-band Low Noise Amplifier (LNA) operating in the GSM 0.9GHz & BLUETOOTH 2.4GHz communication standards. The fully concurrent LNA is designed and simulated in CADENCE using 130nm UMC technology. The dual-band LNA has been designed from the system viewpoint to provide a higher gain at the high band in order to compensate the high-band signal’s extra loss over the air transmission. The current design is especially suitable for use in multi-standard wireless receiver front ends as it saves die area and reduces power consumption by replacing parallel LNAs for each channel frequency. Simulation results indicate a Noise Figure below 2dB and S21 above 14 dB in all frequency bands while drawing 10mA current from a 1.2V power supply.

A concurrent low-area dual band 0.9/2.4 GHz LNA in 0.13µm RF CMOS technology for multi-band wireless receiver

This article presents the design of a low area novel concurrent dual-band LNA operating in the GSM 0.9GHz/BLUETOOTH 2.4GHz communication standards. The concurrent LNA is designed and simulated in CADENCE using 130nm UMC technology. A conventional source degeneration inductor is eliminated for higher signal gain while providing reasonable input impedance. Also by adding a capacitor between the gate and the source of the input transistor, a noise source from the gate resistance is partly suppressed. The output matching network is constructed of shunt peaking. Its easy to achieve matching and reduced chip size. The current design is especially suitable for use in multi-standard wireless receiver frontends as it saves die area and reduces power consumption by replacing parallel LNAs for each channel frequency. Simulation results indicate a Noise Figure below 2dB and S21 above 14 dB in all frequency bands and also input and output return loss are below −10 dB for all desired frequency band while drawing 10mA current from a 1.2V power supply.

PSO-based output matching network for concurrent dual-band LNA

This article presents an original design methodology for the selection of output matching load network for a dual-band Low Noise Amplifier (LNA) that is targeted for the use in the GSM 1.8 GHz and WLAN 2.4 GHz range. A particle swarm optimization (PSO) based technique is used to get the optimized values of the output load network components. The concurrent dual-band LNA is simulated with these entire component values in CADENCE with CMOS 0.18μm technology.

A 1.5–7.5GHz low power low noise amplifier (LNA) design using subthreshold technique for Wireless Sensor Network (WSN) application

A novel wide band low power low noise amplifier using subthreshold technique is presented in this paper. This LNA built with Common-Gate (CG) input stage for wide band input matching and a Common Source (CS) - Common Gate (CG) cascode stage for gain boosting. Power reduction is achieved by driving the front end CG transistor in sub-threshold region and input matching is done by LC circuit instead of traditional CG method (Rs=1/gm). The circuit is simulated using Spectra-RF simulator in 0.18μm CMOS technology, and achieved 13.5-14.5 dB (7.5 to 8.5 dB + 6dB loss in buffer) gain over entire band of 1.5-7.5GHz with a 5-10.5dB NF while consuming 4.9mW of power from 1.8V supply.

Noise-cancelled subthreshold UWB LNA for Wireless Sensor Network application

In this paper, a low power, noise-cancelling subthreshold Ultra ideband (UWB) Low Noise Amplifier (LNA) is presented. In this work subthreshold driven Common Gate (CG) input stage is modified to provide wideband input matching and a current reuse noise cancelling technique is introduced to improve noise performance. Additionally, substantial reduction in power consumption is obtained by driving the MOS devices in subthreshold region. Circuit is simulated using Spectre simulator in UMC 180nm CMOS technology and achieved a gain of 12-13.2 dB (6-7.2 dB + 6dB loss in buffer) with a noise figure of 4-5dB over the band of 1.5-8.5 GHz. Proposed circuit consumes only 1.4mW from 1.5V supply. Hence the proposed circuit topology is very useful for WSN application.

A gain boosted fully concurrent dual-band interstage matched LNA operating in 900 MHz/2.4 GHz with sub-2dB Noise Figure

This paper features the design and detailed analysis of a fully concurrent dual-band Low Noise Amplifier (LNA) operating in the GSM 0.9GHz & BLUETOOTH 2.4GHz communication standards having an inter-stage matching inductor. An interstage inductor between the common source stage and the common gate stage is used to increase power gain. In this work, all the circuit components are considered on-chip. The results show that the proposed topology increases the overall gain. The concurrent LNA is designed and simulated in CADENCE using 130nm UMC technology. The current design is especially suitable for use in multi-standard wireless receiver frontends. Simulation results indicate a Noise Figure below 4dB and S21 above 14 dB in all frequency bands while drawing 10mA current from a 1.2V power supply.

A Tuneable CMOS Pulse Generator for Detecting the Cracks in Concrete Walls

A CMOS impulse generator was designed as a part of Ultra Wide Band (UWB) wireless communication system. An input square wave signal is delayed by using differential pairs and then XORed with the input signal to produce short duration pulses. An RLC circuit works as a Band Pass Filter (BPF) used to generate Gaussian monopulse from the obtained short duration pulses. It operates with center frequency at 4.782 GHz and -3dB band width of 20.36 GHz. The output peak to peak amplitude of the signal is 44.11 mV with pulse duration of 300 picoseconds. The UWB pulse generator has been simulated in 0.18μm CMOS technology.

A low-cost multi-phase 3A buck converter with improved ripple cancellation for wide supply range

This paper proposes a novel method for ripple cancellation in multi-phase converters. Unlike the conventional multi-phase converter, the proposed topology can cancel the ripple irrespective of the duty ratios. The proposed topology is designed to give 3.3V output for wide supply range of 4.5 to 18V and load range of 0 to 3A in AMS 0.35um high-voltage CMOS process. Transistor level simulation results validate that the proposed method can reduce the ripple by 80% in a multi-phase converter. Cancelling the current ripple at the output allows the inductors and capacitors to be sized much smaller compared to the state of the art reported designs.

Automated environment aware nW FOCV — MPPT controller for self-powered IoT applications

This paper presents, a complete energy harvesting system with improved implementation of Fractional Open Circuit Voltage (FOCV) technique, to mitigate obligation of using off chip sampling capacitor, gratuitous periodic open circuit operation for Maximum Power Point Extraction (MPP) from solar cell. A possible solution to minimize the reverse current in solar cell due to abrupt decline in irradiance is also proposed. Thus, usual off-chip sampling capacitance can be effectively replaced by on-chip capacitance as low as 3.75pF. Entire system is implemented in 180nm CMOS technology and the proposed blocks consumes 0.675mm × 0.425mm area and an average power of 340nW.

Low Power Personalized ECG Based System Design Methodology for Remote Cardiac Health Monitoring

This paper describes a mixed-signal electrocardiogram (ECG) system for personalized and remote cardiac health monitoring. The novelty of this paper is fourfold. First, a low power analog front end with an efficient automatic gain control mechanism, maintaining the input of the ADC to a level rendering optimum SNR and the enhanced recyclic folded cascode opamp used as an integrator for ΣΔ ADC. Second, a novel on-the-fly PQRST boundary detection (BD) methodology is formulated for finding the boundaries in continuous ECG signal. Third, a novel low-complexity ECG feature extraction architecture is designed by reusing the same module present in the proposed BD methodology. Fourth, the system is having the capability to reconfigure the proposed low power ADC for low (8 b) and high (12 b) resolution with the use of the feedback signal obtained from the digital block when it is in processing. The proposed system has been tested and validated on patients data from PTBDB, CSEDB, and in-house IIT Hyderabad Data Base (IITHDB) and we have achieved an accuracy of 99% upon testing on various normal and abnormal ECG signals. The whole system is implemented in 180-nm technology resulting in 9.47-μW (at 1 MHz) power consumption and occupying 1.74-mm2 silicon area.