Tarun Kumar Gupta

Ultra-low power FinFET-based domino circuits

ABSTRACT Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.

Carbon NanoTube based logic gates structure for low power consumption at nano-scaled era

As day by day continuing research in the field of nanotechnology, the CMOS manufacturing process scaled down in nano-dimensions at the cost of severe process variations and high leakage current which resulting large power dissipation. Therefore the leakage current and power dissipation becomes increasingly more focused in VLSI circuit design. Carbon NanoTube Field Effect Transistor (CNFETs) is suited best alternatives to the conventional CMOS based devices. During various simulation results, unexpected reduction in process variation, ultra low (nano-scaled) power memory devices and superior improvement of Noise Margin, propagation delay, write-read margin and its stability is found. CNFETs based logic gates are compared with Conventional CMOS and FinFET based logic gates in respect to delay and power consumption.

A Novel Leakage Reduction Technique for Ultra-Low Power VLSI Chips

The modern portable devices demand ultra-low power consumption due to the limited battery size. With each new generation, the need of more transistors on the same chip is increasing due to the increased functionality. The leakage causes static power consumption is exceeding the dynamic power in the sub-nanometer designs. Therefore, effective leakage reduction technique is required to minimize the power consumption. In this paper, we have explored the existing leakage reduction techniques and propose a new leakage reduction technique that provides significant reduction in the leakage without significant area/power overhead. The simulation results on Synopsys HSPIC shows that that proposed leakage reduction technique provides 10 % reduction in leakage over the existing leakage reduction technique in the literature.

A Low leakage domino logic circuit for Wide Fan-in gates using CNTFET

A carbon nanotube field effect transistor (CNTFET) emerged as an alternative to the complementary metal oxide semiconductor (CMOS) for implementing low-power high-speed very-large-scale integration circuits. In this study, the CNTFET technology is discussed that has faster switching speed and high-carrier mobility as compared with the CMOS technology. A new technique ultra-low power dynamic node driven transistor domino logic is proposed for designing low-power domino logic circuits. 2, 4, 8 and 16 input logic gates are simulated using the proposed and existing techniques. Simulation is done on an H-Spice Stanford CNFET 32 nm model at a clock frequency of 200 MHz using the CNTFET technology. The proposed technique shows a maximum power reduction of 57.14% and a maximum delay reduction of 50.24% as compared with the current mirror footed domino logic technique in CNTFET technology. The proposed technique has a maximum power reduction of 96.61% in the CNTFET technology as compared with its counterpart in the CMOS technology for the two-input OR gate. The proposed technique shows a maximum improvement of 1.39× in unity noise gain as compared with the conditional stacked keeper domino logic technique for 16 input OR gates in the CNTFET technology at 200 MHz.

Leakage Power Reduction Technique by Using Multigate FinFET in DSM Technology

Leakage power dissipation is the dominant contributor to total power dissipation today in CMOS integration design. Scaling is the prime thrust for development of CMOS circuits, which increases in the number of faults and leakage current in manometer scale in ultra low power circuit design. Here, in this paper we first reviewed the leakage power of various gates and highlight their merits and short come. FinFET technology completely substitute the CMOS to maintain the Mores law of scaling, next generation is of CNTFET which replaces the FinFET technology in term of scaling. We have calculated various parameters of basic logic gates like dynamic power, static power, delay, PDP and validation of results we have also implemented over C17 (ISCAS 85) benchmark circuit. Extensive HSPICE simulator on some basic gates and benchmark circuit by using SG and LP mode of FinFET and CNTFET technology at different temperature by using 32 nm Berkley Predictive Technology Module (BPTM), with supply voltage of 0.9 V at 100 MHz frequency.

New Leakage Reduction Techniques for FinFET Technology with Its Application

This paper describes three novel techniques such as drain gating PMOS transistor (DGPT), drain gating NMOS transistor (DGNT) and drain gating NMOS–PMOS transistor (DGNPT) for mitigation of leakage power, which are proposed to be used for low-power (LP) applications. The proposed techniques have leakage controlling sleep transistor inserted with sleep signal between pull-up and pull-down networks for reducing the leakage power. Simulation results are derived by HSPICE tool with PTM model for FinFET process fabrication at 32nm technology node at 25∘C and 110∘C temperatures. The proposed techniques are applied on standard and benchmark circuits, then these circuits are implemented on FinFET technology in short-gate (SG) and LP modes at 10MHz frequency. Simulation results show that the maximum reduction in leakage power by the proposed technique DGPT for two-input NAND gate is 99.34% in SG mode and in LP mode it is 99.83% at 25∘C. DGNT technique gives the maximum saving in leakage power consumption of 97.17% ...

Optimization Techniques for High Performance 9T SRAM Cell Design

The new era begin to understand these beyond semiconductor CMOS devices, and circuit capabilities, to test and analysis the performance of CNTFET based structures compared to conventional silicon processes. These new devices can replace silicon in logic, analog, memory and data converters applications. The most close to the design of CNTFET based include the carbon-based options of graphene and carbon nanotube technologies, and also compound semiconductor-based Carbon nanotubes FET (CNTFETs). The study of high performance nine transistor static random access memory arrays and its optimization in 9-nm CNTFET technology are presented and comparative study done with the conventional six-transistors (6T) and previously issued eight-transistor (8T) Static RAM cell. The 9T CNTFET Static RAM cell provides same read speed comparatively 6T and 8T but has read data stability is enhanced by 1.56×. The proposed new memory cell consumes 53.40–19.17 % low leakage power comparatively the 6T and 8T Static RAM cell, respectively.

Techniques for Designing Analog Baseband Filter: A Review

Different Design Techniques for implementing the Analog Baseband filter are presented in this paper. The baseband filter is classified on the basis of approximation techniques, type of component, technology and type of signal used. These techniques are compared on the basis of CMOS technology, minimum cutoff frequency, filter order, power consumption, supply voltage and integrating capacitance. The filters compared in this paper are active continuous time analog filters.

Leakage Power Reduction Technique by Using FinFET Technology in ULSI Circuit Design

Deep Sub Micron (DSM) technology demands for lower supply voltage, reduced threshold voltage and high transistor density which leads to exponentially increase in leakage power when circuit is in standby mode. Here review of FinFET transistor along with existing low power techniques in DSM circuits like sleep, LECTOR etc. are done. Then Lector with FinFET technology circuit is proposed. This work evaluates the impact of FinFET technology, which has huge potential to replace bulk CMOS in DSM range. Performance of proposed technique is investigated in terms of dynamic power, delay, Power Delay Product (PDP) and leakage power dissipation. The proposed techniques has leakage controlling sleep transistor inserted over pull up and pull down network which significantly reducing the leakage power by using HSPICE simulator in 32 nm FinFET technology at 25 and 110 °C with CL = 1 pF at 100 MHz frequency.

A novel efficient adiabatic logic design for ultra low power

With the continuously growing quest for miniaturization of circuit technology, one of the prime focuses of the research has shifted in the direction of ultra low power circuit designs. Over the years, adiabatic circuit designs have been studied and found to be effective in achieving low power in VLSI circuits. This paper briefs some of the adiabatic logic families such as ECRL, 2N-2N2P and PFAL. And presents a new adiabatic logic circuit based on PFAL logic family. This paper aims at comparing the effectiveness of proposed adiabatic logic circuit, in terms of power dissipation, over other adiabatic logic families by simulating different logic gates using these logic families. All the simulations are done using HSPICE Simulator at 65nm technology at different frequency range. Comparative results are presented by different bar graphs plotted at different frequencies, which shows least power dissipation for the proposed logic circuit.