Kavita Khare

Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection

This paper presents an area-time efficient CORDIC algorithm that completely eliminates the scale-factor. By suitable selection of the order of approximation of Taylor series the proposed CORDIC circuit meets the accuracy requirement, and attains the desired range of convergence. Besides we have proposed an algorithm to redefine the elementary angles for reducing the number of CORDIC iterations. A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. The proposed CORDIC processor provides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Compared to the existing recursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device.

Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation

This paper presents a novel completely scaling-free CORDIC algorithm in rotation mode for hyperbolic trajectory. We use most-significant-1 bit detection technique for micro-rotation sequence generation to reduce the number of iterations. By storing the sinh/cosh hyperbolic values at octant boundaries in a ROM, we can extend the range of convergence to the entire coordinate space. Based on this, we propose a pipeline hyperbolic CORDIC processor to implement a direct digital synthesizer (DDS). The DDS is further used to derive an efficient arbitrary waveform generator (AWG), where a pseudo-random number generator modulates the linear increments of phase to produce random phase-modulated waveform. The proposed waveform generator requires only one DDS for generating variety of modulated waveforms, while existing designs require separate DDS units for different type of waveforms, and multiple DDS units are required to generate composite waveforms. Therefore, area complexity of existing designs gets multiplied with the number of different types waveforms they generate, while in case of proposed design that remains unchanged. The proposed AWG when mapped on Xilinx Spartan 2E device, consumes 1076 slices and 2016 4-input LUTs. The proposed AWG involves significantly less area and lower latency, with nearly the same throughput compared to the existing CORDIC-based designs.

Phase frequency detector of delay locked loop at high frequency

This paper present the design scheme of a phase frequency detector (PFD) which uses domino logic. The PFD is capable of working in gigahertz range frequency with reduced the dead zone as the reset path is increased using the inverters. The linear detection range is also increased of this PFD. In particular maximum operating frequency of PFD is discussed. The proposed PFD has simple structure with using 26 transistors. It can be operated at 1.8 V supply using 0.18 micron CMOS technology. This PFD is designed for RF range delay locked loop.

Analysis of low voltage rail-to-rail CMOS operational amplifier design

As the supply voltage to a standard CMOS op-amp is reduced, the input common mode range and the output swing get reduced drastically. Special circuits have to be used to raise them up to rail-to-rail supply voltage. This paper describes the design of a low-voltage CMOS rail-to-rail input output operational amplifier. Analysis of input signal compression circuitry that compresses rail-to-rail input signals to the input range of the following folded-cascode operational amplifier is done. The input signal compression circuitry and the following folded-cascode operational amplifier together comprise an input-output rail-to-rail operational amplifier. It is concluded that Cadence Spectre simulation tool with 0.18-mum CMOS validates the operation of the rail-to-rail CMOS amplifier with supply voltage of 1 V and bias current of 3.1 muA.

VLSI design and analysis of low power 6T SRAM cell using cadence tool

CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. This paper implements 6T SRAM cell with reduced read and write time, area and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result in slower and more energy hungry memories.. In this paper Two SRAM cell is being designed for 4 Kb of memory core with supply voltage 1.8 V. A technique of global bit line is used for reducing the power consumption and increasing the memory capacity.

Ultra-low power FinFET-based domino circuits

ABSTRACT Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.

Concept, Design, and Implementation of Reconfigurable CORDIC

This brief presents the key concept, design strategy, and implementation of reconfigurable coordinate rotation digital computer (CORDIC) architectures that can be configured to operate either for circular or for hyperbolic trajectories in rotation as well as vectoring-modes. It can, therefore, be used to perform all the functions of both circular and hyperbolic CORDIC. We propose three reconfigurable CORDIC designs: 1) a reconfigurable rotation-mode CORDIC that operates either for circular or for hyperbolic trajectory; 2) a reconfigurable vectoring-mode CORDIC for circular and hyperbolic trajectories; and 3) a generalized reconfigurable CORDIC that can operate in any of the modes for both circular and hyperbolic trajectories. The reconfigurable CORDIC can perform the computation of various trigonometric and exponential functions, logarithms, square-root, and so on of circular and hyperbolic CORDIC using either rotation-mode or vectoring-mode CORDIC in one single circuit. It can be used in digital synchronizers, graphics processors, scientific calculators, and so on. It offers substantial saving of area complexity over the conventional design for reconfigurable applications.

Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC Pipeline

Filtering being one of the most important modules in signal processing paradigm, this paper presents an FPGA implementation of various window-functions using CORDIC algorithm to minimize area-delay product. The existing window-architecture uses a linear CORDIC processor in series with circular CORDIC processor, that results in a long pipeline. Firstly, we replace the linear CORDIC with multiple optimized shift-add networks to reduce area and pipeline depth. Secondly, the conventional circular CORDIC processor is replaced by a completely scaling-free CORDIC processor to further improve the area-time efficiency of the existing design. As a result, the proposed window-architecture, on an average requires approximately 64.34% less pipeline stages and saves upto 48% area. Both the existing and the proposed window-architecture are capable of generating Hanning, Hamming and Blackman window families.

High Speed FPGA Implementation of FIR Filter for DSP Applications

algorithms. The advantages of the FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips, lower costs than an application specific integrated circuit (ASIC) for moderate volume applications, and more flexibility than the alternate approaches. Since many current FPGA architectures are in-system programmable, the configuration of the device may be changed to implement different functionality if required. This paper describes an approach to the implementation of digital filter based on field programmable gate arrays (FPGAs) which is flexible and provides performance comparable or superior to traditional approaches, low-power, area-efficient re-configurable digital signal processing architecture that is tailored for the realization of arbitrary response Finite impulse response (FIR) filters.

CORDIC-based window implementation to minimise area and pipeline depth

Filtering is one of the most important modules in signal processing paradigm. This study presents a field-programmable gate array implementation of various window functions using coordinate rotation digital computer (CORDIC) algorithm to minimise area-delay product. First, the authors modify the Taylor series approximation order used in the scaling-free CORDIC, to completely eliminate the scale-factor and, yet, preserve the range of convergence spanning across the entire coordinate space. Secondly, the authors propose a new generalised technique for micro-rotation sequence identification to reduce the number of iterations required by the pipelined CORDIC processor. Then, this circular CORDIC processor is used to realise window functions. The existing window architecture uses a linear CORDIC processor in series with circular CORDIC processor, resulting in long pipeline. The authors replace the linear CORDIC with multiple optimised shift-add networks to reduce area and pipeline depth. As a result, the proposed window architecture, on an average requires approximately 64.34% less pipeline stages and saves up to 48% area. The authors have designed the processor to implement Hanning, Hamming and Blackman window families. The implementation of the proposed architecture is detailed in this study.