Tatiana Kalganova

Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness

We use evolutionary search to design combinational logic circuits. The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells whose dimension is defined by the circuit layout. The main idea of this approach is to improve quality of the circuits evolved by the genetic algorithm (GA) by reducing the number of active gates used. We accomplish this by combining two ideas: 1) using multi-objective fitness function; 2) evolving circuit layout. It will be shown that using these two approaches allows us to increase the quality of evolved circuits. The circuits are evolved in two phases. Initially the genome fitness is given by the percentage of output bits that are correct. Once 100% functional circuits have been evolved, the number of gates actually used in the circuit is taken into account in the fitness function. This allows us to evolve circuits with 100% functionality and minimise the number of active gates in circuit structure. The population is initialised with heterogeneous circuit layouts and the circuit layout is allowed to vary during the evolutionary process. Evolving the circuit layout together with the function is one of the distinctive features of proposed approach. The experimental results show that allowing the circuit layout to be flexible is useful when we want to evolve circuits with the smallest number of gates used. We find that it is better to use a fixed circuit layout when the objective is to achieve the highest number of 100% functional circuits. The two-fitness strategy is most effective when we allow a large number of generations.

Bidirectional incremental evolution in extrinsic evolvable hardware

Evolvable Hardware (EHW) has been proposed as a new technique to design complex systems. Often, complex systems turn out to be very difficult to evolve. The problem is that a general strategy is too difficult for the evolution process to discover directly. This paper proposes a new approach that performs incremental evolution in two directions: from complex system to sub-systems and from sub-systems back to complex system. In this approach, incremental evolution gradually decomposes a complex problem into some sub-tasks. In a second step, we gradually make the tasks more challenging and general. Our approach automatically discovers the sub-tasks, their sequence as well as circuit layout dimensions. Our method is tested in a digital circuit domain and compared to direct evolution. We show that our bidirectional incremental approach can handle more complex, harder tasks and evolve them more effectively, then direct evolution.

Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits

In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed method consists of four main stages. The first stage is concerned with the use of genetic algorithms (GA) for the state assignment problem to compute optimal binary codes for each symbolic state and construct the state transition table of finite state machine (FSM). The second stage defines the subcircuits required to achieve the desired functionality. The third stage evaluates the subcircuits using extrinsic Evolvable Hardware (EHW). During the fourth stage, the final circuit is assembled. The obtained results compare favourably against those produced by manual methods and other methods based on heuristic techniques.

Some Aspects of an Evolvable Hardware Approach for Multiple-Valued Combinational Circuit Design

In this paper a gate-level evolvable hardware technique for designing multiple-valued (MV) combinational circuits is proposed for the first time. In comparison with the decomposition techniques used for synthesis of combinational circuits previously employed, this new approach is easily adapted for the different types of MV gates associated with operations corresponding to different algebra types and can include other more complex logical expressions (e.g. singlecontrol MV multiplexer called T-gate). The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells. The experimental results show how the success of genetic algorithm depends on the number of columns, the number of rows in circuit structure and levels-back parameter (the number of columns to the left of current cell to which cell input may be connected). We show that the choice of the set of MV gates used radically affects the chances of successful evolution (in terms of number of 100% functional solutions found).

On evolution of relatively large combinational logic circuits

Evolvable hardware (EHW) (Yao and Higuchi, 1999) is a technique introduced to automatically design circuits where the circuit configuration is carried out by evolutionary algorithms. One of the main difficulties in using EHW to solve real-world problems is the scalability. Until now, several strategies have been proposed to avoid this problem, but none of them completely tackle the issue. In this paper three different methods for evolving the most complex circuits have been tested for their scalability. These methods are bi-directional incremental evolution (SO-BIE); generalised disjunction decomposition (GD-BIE) and evolutionary strategies (ES) with dynamic mutation rate. In order to achieve the generalised conclusions the chosen approaches were tested using multipliers, traditionally used in EHW, but also logic circuits taken from MCNC (Yang, 1991) benchmark library and randomly generated circuits. The analysis of the approaches demonstrated that PLA-based ES is capable of evolving logic circuits of up to 12 inputs. The use of SO-BIE allows the generation of fully functional circuits of 14 inputs and GD-BIE is estimated to be able to evolve circuits of 21 inputs.

An Extrinsic Function-Level Evolvable Hardware Approach

The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in first time. The new representation of logic gate in extrinsic EHW allows us to describe behaviour of any multi-input multi-output logic function. The circuit is represented in the form of connections and functionalities of a rectangular array of building blocks. Each building block can implement primitive logic function or any multi-input multi-output logic function defined in advance. The method has been tested on evolving logic circuits using half adder, full adder and multiplier. The effectiveness of this approach is investigated for multiple-valued and binary arithmetical functions. For these functions either method appears to be much more efficient than similar approach with two-input one-output cell representation.

A Novel Genetic Algorithm for Evolvable Hardware

Evolutionary algorithms are used for solving search and optimization problems. A new field in which they are also applied is evolvable hardware, which refers to a self-configurable electronic system. However, evolvable hardware is not widely recognized as a tool for solving real-world applications, because of the scalability problem, which limits the size of the system that may be evolved. In this paper a new genetic algorithm, particularly designed for evolving logic circuits, is presented and tested for its scalability. The proposed algorithm designs and optimizes logic circuits based on a Programmable Logic Array (PLA) structure. Furthermore it allows the evolution of large logic circuits, without the use of any decomposition techniques. The experimental results, based on the evolution of several logic circuits taken from three different benchmarks, prove that the proposed algorithm is very fast, as only a few generations are required to fully evolve the logic circuits. In addition it optimizes the evolved circuits better than the optimization offered by other evolutionary algorithms based on a PLA and FPGA structures.

Improving EHW performance introducing a new decomposition strategy

This paper describes a new type of decomposition strategy for Evolvable Hardware, which tackles the problem of scalability. Several logic circuits from the MCNC benchmark have been evolved and compared with other Evolvable Hardware techniques. The results demonstrate that the proposed method improves the evolution of logic circuits in terms of time and fitness function in comparison with BIE and standard EHW.

Constrained and Unconstrained evolution of “ LCR” low-pass filters with oscillating length representation

The unconstrained evolution has already been applied in the past towards design of digital circuits, and extraordinary results have been obtained, including generation of circuits with smaller number of electronic components. In this paper both constrained and unconstrained evolutions, blended with oscillating length genotype sweeping strategy, are applied towards design of analogue “ LCR” circuits. The comparison of both evolutions is made and the promising results are obtained. The new algorithm has produced the best results in terms of quality of the circuits evolved and evolutionary resources required. It differs from previous ones by its simplicity and represents one of the first attempts to apply Evolutionary Strategy towards the analogue circuit design. The obtained results are compared in details with low-pass filters previously designed.

Multiple Traffic Signal Control Using A Genetic Algorithm

Optimising traffic signal timings for a multiple-junction road network is a difficult but important problem. The essential difficulty of this problem is that the traffic signals need to coordinate their behaviours to achieve the common goal of optimising overall network delay. This paper discusses a novel approach towards the generation of optimal signalling strategies, based on the use of a genetic algorithm (GA). This GA optimises the set of signal timings for all junctions in network. The different efficient red and green times for all the signals are determined by genetic algorithm as well as the offset time for each junction. Previous attempts to do this rely on a fixed cycle time, whereas the algorithm described here attempts to optimise cycle time for each junction as well as proportion of green times. The fitness function is a measure of the overall delay of the network. The resulting optimised signalling strategies were compared against a well-known civil engineering technique, and conclusions drawn.