Tatsuji Ashitani

6.7 A 1.2e− temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA

This paper presents a 1.2e-, 3D-stacked CMOS image sensor (CIS) for mobile applications. A key motivation for using a stacked configuration is to minimize the chip area. Also, since numerous components must be integrated into the bottom chip, a scaled 65nm CMOS process is adopted for the bottom chip. The developed CIS features 1.2e- temporal noise with extremely high power efficiency by employing a multiple-sampling (MS) technique. A 2nd-order incremental ΔΣ ADC with inverter-based switched-capacitor integrator realizes the MS technique with low power [1]. However, an exponential number of samples are required to reduce the quantization noise, and conversion speed worsens with higher bit resolution. An extended counting ADC, which is a blend of folding integration and cyclic ADC, attains high resolution with reduced conversion time [2-3]. However, an op-amp with high open-loop gain is required for good linearity and column-to-column matching characteristics, which increases power consumption. Also it is not suitable for scaled CMOS technology. An alternative approach is a single-slope (SS) based MS technique [4], in which two SS-ADCs convert the same pixel signal, and the readout signal is averaged in the digital domain, but the noise improvement is limited to -3dB and the power consumption and area occupation are roughly doubled.

A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication

A 1.4Mpixel CMOS image sensor (CIS) with multiple row-rescan (MRR) based data sampling for optical camera communication (OCC) is presented. The CIS achieves a data sampling rate at a row-scan rate of 51kS/s even with a frame rate of 30fps, a pixel size of 2.2mm × 2.2mm by multiply rescanning the rows at a modulated LED spot. The detectable minimum LED size projected onto the CIS becomes 13.2mm × 13.2mm. The MRR could be a practical solution for IEEE 802.15.SG7a OCC.

Writing Power Balance Control Method for HD DVD

We have developed a new writing condition adjustment method for HD DVD. The conventional adjustment method developed for HD DVD has local optimality because the conventional method cannot be used to control the asymmetry of the readout signal. To solve this problem, we have proposed a new method that can be used to optimize the asymmetries of each symbol of the readout signal by manipulating the writing pulse width of each symbol. Experimental results show that the proposed method can be used to optimize the writing pulse condition with lower local optimality than the conventional method and can enlarge the writing power margin. Thus, we can realize better productivity and stability in the drives because more variations in terms of discs and drives are possible.

Writing Power Optimization Method for Rewritable Optical Media

For rewritable optical media, overwriting repeatability is a very important index of performance. In HD DVD-re-recordable (RW) media, the direct overwrite (DOW) margin becomes narrower than that in conventional rewritable media, because the recording density becomes high. Therefore, it is difficult to obtain sufficient DOW characteristics by conventional writing power control methods. In this study, we investigate the degradation factor of DOW characteristics in HD DVD-RW media and develop a new writing power optimization method, which involves detection of changes in space level after DOW. As a result of optimizing writing power of HD DVD-RW media by this new method, the partial response signal-to-noise ratio (PRSNR) after 1000 DOW cycles is about 24 in commercial drives, and it is much more improved than that obtained by conventional methods. Accordingly, it is possible to realize optical disk drives with high recording performance for rewritable optical media.