Tatsuo Ozeki

Highly resistive GaN layers formed by ion implantation of Zn along the c axis

Highly resistive layers are formed by the implantation of Zn ion along the c axis of GaN and AlGaN/GaN epitaxial layers. Heavy ions such as Zn have been desirable for the formation of highly resistive layers, because ions effectively transferred their energy to the crystal atoms rather than the electrons in GaN. A sheet resistance Rs as high as 3.8×1011 Ω/sq was obtained on GaN layers after the ion implantation. Rs increased up to 2.2×1013 Ω/sq after the annealing at 500 °C for 300 s in an N2 atmosphere. The thermal activation energy Er for this sample was 0.67 eV. It was found that the experimental data in current–voltage characteristics were fitted to the equation included the Poole–Frenkel current and resistive (ohmic) current. The difference of Rs between the as-implanted and 500 °C annealed samples was due to the Poole–Frenkel current. The Poole–Frenkel current overcame the resistive one, and dominated the current mechanism in the case of the samples annealed at 200 °C or less. On the other hand, for...

Improvement of DC and RF Characteristics of AlGaN/GaN High Electron Mobility Transistors by Thermally Annealed Ni/Pt/Au Schottky Gate

A thermally annealed Ni/Pt/Au metal structure was employed as the gate contacts of AlGaN/GaN high electron mobility transistors (HEMTs), and their DC and RF performances were investigated. This gate structure markedly improved the Schottky characteristics such as the Schottky barrier height and leakage current. Regarding the DC characteristics, the maximum drain current and off-state breakdown voltage were increased from 0.78 A/mm (Vg=1 V) to 0.90 A/mm (Vg=3 V) due to the improved applicability of the gate voltage and from 108 V to 178 V, respectively, by annealing the gate metals. In addition, a reduction of the transconductance was not observed. Furthermore, even after the deposition of SiNx passivation film, the off-state breakdown voltage remained at a relatively high value of 120 V. Regarding the RF characteristics, the cut-off frequency and maximum oscillation frequency were also improved from 10.3 GHz to 13.5 GHz and from 27.5 GHz to 35.1 GHz, respectively, by annealing the gate metals whose gate length was 1 µm.

Low-cost 320x240 uncooled IRFPA using a conventional silicon IC process

A 320 X 240 uncooled IR focal plane array (IRFPA) with series PN junction diodes fabricated on a silicon-on- insulator (SOI) wafer has been developed. Resistive bolometers, pyroelectric detectors and thermopile detectors have been reported for large scale uncooled IRFPAs, while the detector developed uses the temperature dependence of forward-biased voltage of the diode. The diode has low 1/f noise because it is fabricated on the monocrystalline SOI film which has few defects. The diode is supported by buried silicon dioxide film of the SOI wafer, which becomes a part of a thermal isolated structure by using bulk silicon micromachining technique. The detector contains an absorbing membrane with a high fill factor of 90 percent to achieve high IR absorption, and the readout circuit of the FPA contains a gate modulation integrator to suppress the noise. Low cost IRFPA can be supplied because the whole structure of the FPA is fabricated on commercial SOI wafers using a conventional silicon IC process.

Relation Between Spacing Losses And Level Differences In Laminated Films Heads

A reproduced voltage and the surface level difference between magnetic metal layers and substrates were measured directly. During the measurement of the reproduced voltage, the level difference grows depending on the characteristics of the magnetic tape. The spacing loss is proportional to the level difference. The level difference, therefore, is one of the most important causes of the spacing loss. The same results are found in various magnetic tapes. The spacing losses in recording and in reproducing were measured separately and were found to be proportional to the level difference. The spacing loss factor in reproducing is about two times larger than in recording. >

Low Temperature Deposition of HfO2 Gate Insulator on SiC by Metalorganic Chemical Vapor Deposition

Low temperature deposition of HfO2 films on 4H-SiC(0001) substrates by pulse introduced metalorganic chemical vapor deposition (MOCVD) using tetrakis-diethylamido-hafnium [Hf[N(C2H5)2]4, (TDEAH)] and H2O has been investigated. HfO2 films with relatively low leakage current density of 10-4 A/cm2 were obtained even at a deposition temperature as low as 190 °C. We demonstrate that the HfO2/SiC interface, where the HfO2 was deposited at 190 °C, has lower interface state density than a typical thermally-grown SiO2/SiC interface. It is also shown by X-ray photoelectron spectroscopy (XPS) that the HfO2/SiC structure fabricated at 190 °C has lower SiOx count than the HfO2/SiC structure fabricated at 400 °C.

Fabrication and Performance of 1.2 kV, 12.9 mΩcm2 4H-SiC Epilayer Channel MOSFET

4H-SiC epilayer channel MOSFETs are fabricated. The MOSFETs have an n- epilayer channel which improves the surface where the MOS channel is formed. By the optimization of the epilayer channel and the MOSFET cell structure, an ON-resistance of 12.9 mcm2 is obtained at VG = 12 V (Eox = 2.9 MV/cm). A normally-OFF operation and stable avalanche breakdown is obtained at the drain voltage larger than 1.2 kV. Both the ON-resistance and the breakdown voltage increase slightly with an increase in temperature. This behavior is favorable for high power operation. By the evaluation of the control MOSFETs with n+ implanted channel, the resistivity of the MOS channel is estimated. The MOS channel resistivity is proportional to the channel length and it corresponds to an effective channel mobility of about 20 cm2/Vs.

Fabrication of vertical recording heads

Recording and reproducing characteristics of one-sided access heads are investigated. Optimum structures for recording are determined from the results of head field analyses by the finite element method. The magnetic flux flow into the coil is also calculated. Experimental and calculated results are in good agreement.

PtSi FPA with improved CSD operation

Over the past ten years we have been developing PtSi focal plane arrays (FPAs) using the charge sweep device (CSD). FPAs are going to high resolution and the power of the FPAs are on an upward trend. Now we have developed a low-power CMOS CSD scanner (LOCCS) for a high resolution FPA. The conventional CSD scanner operates at the same frequency as that of the horizontal CCD to prevent fixed pattern noise (FPN), and generates a frequency pulse higher than the minimum requirement. The LOCCS is a kind of CMOS dynamic shift resistor, which generates clock pulses for vertical signal transfer without the low frequency input pulses that cause FPN. Because the LOCCS generates multi-phase clock pulses, the power consumption can be reduced. We have fabricated test devices to evaluate the improved CSD operation by the LOCCS, and confirmed that the devices operate normally and the reduction of power consumption is in good agreement with the theory. We also applied the LOCCS to a 256 by 256 PtSi FPA and obtained thermal images.

Influence Of Insulators On R/w Process In Laminated Films Heads

The influence of insulators on read/write (R/W) process in laminated film heads was investigated by the Bitter method and computer simulations. Some unrecorded areas exist in a recording track, and the areas correspond to the position of insulators at the trailing side. The effective recording width depends on not only the recording current but also the relative positions of insulators at the leading and trailing edges. These results were confirmed by the simulation. In the reproducing process, the loss caused by the insulator is smaller than the ratio of the track width by the insulators thickness. In both R/W characteristics, the laminated film head with inline insulators at both sides of the gap is superior to that with the staggered insulators. >

Switching Characteristics of SiC-MOSFET and SBD Power Modules

Prototype SiC power modules are fabricated using our class 10 A, 1.2 kV SiC-MOSFETs and SiC-SBDs, and their switching characteristics are evaluated using a double pulse method. Switching waveforms show that both overshoot and tail current, which induce power losses, are suppressed markedly compared with conventional Si-IGBT modules with similar ratings. The total switching loss (MOSFET turn-ON loss, turn-OFF loss and SBD recovery loss) of SiC power modules is measured to be about 30% of that of Si-IGBT modules under the generally-used switching condition (di/dt ~250A/μs). The three losses of SiC modules decrease monotonically with a decrease in gate resistance, namely switching speed. The result shows the potential of unipolar device SiC power modules.