Naruhisa Miura

Remarkable Increase in the Channel Mobility of SiC-MOSFETs by Controlling the Interfacial

The impact of a thin SiO₂ layer inserted between Al₂O₃ and SiC on channel mobility in AI₂O₃/SiC MOSFETs was investigated. The remarkable increase in the channel mobility is demonstrated when the SiO₂ thickness is around 1 nm. The thin SiO₂ layer is formed by the thermal oxidation of the SiC substrate at 600 or 800degC in O₂ atmosphere. The peak value of the field-effect mobility in AI₂O₃/SiO₂/SiC MOSFETs is as high as 300 cm² / (V ldr s). On the other hand, when the SiO₂ layer is 2.0 nm, the field-effect mobility drastically reduces to 40 cm²/ (V ldr s), which is most likely due to the high interface trap density as seen in conventional SiO₂/SiC MOSFETs.

\hbox{SiO}_{2}

Highly resistive layers are formed by the implantation of Zn ion along the c axis of GaN and AlGaN/GaN epitaxial layers. Heavy ions such as Zn have been desirable for the formation of highly resistive layers, because ions effectively transferred their energy to the crystal atoms rather than the electrons in GaN. A sheet resistance Rs as high as 3.8×1011 Ω/sq was obtained on GaN layers after the ion implantation. Rs increased up to 2.2×1013 Ω/sq after the annealing at 500 °C for 300 s in an N2 atmosphere. The thermal activation energy Er for this sample was 0.67 eV. It was found that the experimental data in current–voltage characteristics were fitted to the equation included the Poole–Frenkel current and resistive (ohmic) current. The difference of Rs between the as-implanted and 500 °C annealed samples was due to the Poole–Frenkel current. The Poole–Frenkel current overcame the resistive one, and dominated the current mechanism in the case of the samples annealed at 200 °C or less. On the other hand, for...

Layer Between

A thermally annealed Ni/Pt/Au metal structure was employed as the gate contacts of AlGaN/GaN high electron mobility transistors (HEMTs), and their DC and RF performances were investigated. This gate structure markedly improved the Schottky characteristics such as the Schottky barrier height and leakage current. Regarding the DC characteristics, the maximum drain current and off-state breakdown voltage were increased from 0.78 A/mm (Vg=1 V) to 0.90 A/mm (Vg=3 V) due to the improved applicability of the gate voltage and from 108 V to 178 V, respectively, by annealing the gate metals. In addition, a reduction of the transconductance was not observed. Furthermore, even after the deposition of SiNx passivation film, the off-state breakdown voltage remained at a relatively high value of 120 V. Regarding the RF characteristics, the cut-off frequency and maximum oscillation frequency were also improved from 10.3 GHz to 13.5 GHz and from 27.5 GHz to 35.1 GHz, respectively, by annealing the gate metals whose gate length was 1 µm.

\hbox{Al}_{2}\hbox{O}_{3}

Ensuring gate oxide reliability and low switching loss is required for a trench gate SiC-MOSFET. We developed a trench gate SiC-MOSFET with a p-type region, named Bottom P-Well (BPW), formed at the bottom of the trench gate for bottom oxide protection. We can see an effective reduction in the maximum bottom oxide electric field (Eox) and a significant improvement in dynamic characteristics with a grounded BPW, whose dV/dt is 76 % larger than that with a floating BPW due to reduction in gate-drain capacitance (Cgd). The grounded BPW is found to be an effective means of both suppressing Eox and reducing switching loss.

and SiC

SiC-MOSFETs provide superior performance for next generation power electronics systems. High threshold voltage 600 V SiC-MOSFETs were realized utilizing a reoxidation process, which drastically improves a tradeoff between an ON-resistance and a threshold voltage. Low-loss SiC-MOSFETs with a 1200 V/100-A rating have been developed. Using the developed SiC-MOSFETs, 1200 V/800-A high-power full SiC module with an ON-resistance as low as 2.9 mΩ at 150 °C was successfully fabricated. The high-power module markedly reduces power loss especially at high carrier frequency. Large-area 3300 V SiC-MOSFETs with an ON-resistance of 52 mΩ at 175 °C exhibit an adequate reverse bias safe operating area and 3300 V SiC-MOSFETs screened by applying a body diode current stress show stable characteristics under a continuous current through their body diode for 1000 h.

Highly resistive GaN layers formed by ion implantation of Zn along the c axis

We have successfully developed 4H-SiC devices including metal–oxide–semiconductor field-effect transistors (MOSFETs) and Schottky barrier diodes (SBDs) with a rated voltage of 3.3 kV. The conduction loss of the SiC-MOSFET was reduced to as low as that of the Si-insulated gate bipolar transistor (IGBT) by the n-type doping of the junction field-effect transistor region (JFET doping). The JFET doping technique is effective in reducing the temperature coefficient of resistance in the JFET region, leading to the decreased on-resistance of the SiC-MOSFET at high temperatures. These devices have been applied to 3.3 kV/1500 A modules for the worlds first all-SiC traction inverter. The switching loss of the new traction inverter system is approximately 55% less than that of a conventional inverter system incorporating Si modules.

Improvement of DC and RF Characteristics of AlGaN/GaN High Electron Mobility Transistors by Thermally Annealed Ni/Pt/Au Schottky Gate

Ultrahigh channel mobility is demonstrated for 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with Al2O3 gate insulators fabricated at low temperatures by metal-organic chemical-vapor deposition. Relatively high field effect channel mobility of 64cm2∕Vs is obtained when the Al2O3 gate insulator is deposited at 190°C. Furthermore, extremely high field effect mobility of 284cm2∕Vs was obtained for a MOSFET fabricated with an ultrathin thermally grown SiOx layer inserted between the Al2O3 and SiC.

4H-SiC Trench MOSFET with Bottom Oxide Protection

The reliability of CVD gate oxide was investigated by CCS-TDDB measurement and compared with thermally grown gate oxide. Although the QBD of thermal oxide becomes smaller for the larger oxide area, the QBD of CVD oxide is almost independent of the investigated gate oxide area. The QBD at F = 50% of CVD oxide, 3 C/cm2, is two orders of magnitude larger for the area of 1.96×10-3 cm2 at 1 mA/cm2 compared to that of thermal oxide. More than 80% of the CVD oxide breakdown occurs at the field oxide edge and more than 70% of the thermal oxide breakdown in the inner gate area. These results suggest that the lifetime of CVD oxide is hardly influenced by the quality of SiC, while the defects and/or impurities in SiC affect the lifetime of thermally grown oxide.

Characteristics of 600, 1200, and 3300 V Planar SiC-MOSFETs for Energy Conversion Applications

We have fabricated and characterized MOS capacitors and lateral MOSFETs using Al2O3 as a gate insulator. Al2O3 films were deposited by metal-organic chemical vapor deposition (MOCVD) at temperatures as low as 190 oC using tri-ethyl-aluminum and H2O as precursors. We first demonstrate from the capacitance – voltage (C-V) measurements that the Al2O3/SiC interface has lower interface state density than the thermally-grown SiO2/SiC interface. No significant difference was observed between X-ray photoelectron spectroscopy (XPS) Si 2p spectrum from the Al2O3/SiC interface and that from the SiC substrate, which means the SiC substrate was not oxidized during the Al2O3 deposition. Next, we show that the fabricated lateral SiC-MOSFETs with Al2O3 gate insulator have good drain current – drain voltage (ID-VD) and drain current – gate voltage (ID-VG) characteristics with normally-off behavior. The obtained peak values of field-effect mobility (μFE) are between 68 and 88 cm2/Vs.

3.3 kV/1500 A power modules for the world’s first all-SiC traction inverter

Inversion-type 4H-SiC power MOSFETs using p-body implanted with retrograde profiles have been fabricated. The Al concentration at the p-body surface (Nas) is varied in the range from 5×1015 to 2×1018 cm-3. The MOSFETs show normally-off characteristics. While the Ron is 3 cm2 at Eox = (Vg-Vth)/dox ≅ 3 MV/cm for the MOSFET with the Nas of 2×1018 cm-3, the Ron is reduced by a decrease in the Nas and 26 mcm2 is attained for the device with the Nas of 5×1015 cm-3. The inversion channel mobility and threshold voltage are improved with a decrease in the Nas. By modifying the structural parameter of the MOSFET, a still smaller Ron of 7 mcm2 is achieved with a blocking voltage of 1.3 kV.