Tatsuro Nagahara

Image Reversal Trilayer Process Using Standard Positive Photoresist

Conventional trilayer schemes alleviate the decreasing photoresist budgets as well as satisfy the antireflection issues associated with high NA imaging. However, a number of challenges still exist with standard trilayer processing, most notable among which is the lack of broad resist compatibility and trade-offs associated with improving Si content, such as stability and lithography performance. One way to circumvent these issues is to use a silicon hard mask coated over a photoresist image of reverse tone to the desired pattern. Feasibility of this image reversal trilayer process was demonstrated by patterning of trenches and contact holes in a carbon hard mask from line and pillar photoresist images, respectively. This paper describes the lithography, pattern transfer process and materials developed for the image reversal trilayer processing.

Process enhancements for negative tone development (NTD)

The negative tone development (NTD) process has proven benefits for superior imaging performance in 193nm lithography. Shrink materials, such as AZ® RELACS® have found widespread use as a resolution enhancement technology in conventional 248nm (DUV), 193 nm dry (ArF) and 193 nm immersion (ArFi) lithography. Surfactant rinses, such as AZ® FIRM® are employed as yield enhancement materials to improve the lithographic performance by avoiding pattern collapse, eliminating defects, and improving CDU. This paper describes the development and recent achievements obtained with new shrink and rinse materials for application in NTD patterning processes.

Chemical shrink materials and process for negative tone development (NTD) resist

Negative tone shrink materials (NSM) suitable for resolution enhancement of negative tone development (NTD) 193nm immersion resists have been developed. While this technology is being applied to integrated circuits (IC) manufacturing, reduction of shrink differences between isolated and dense (ID) CDs also called as shrink ID bias is the challenge to meet wide-spread applications. In this paper, we present the effects of resist thermal flow, proximity effects of DUV exposure, flood exposure of after developed image (ADI) on the NSM shrink. High mixing bake (MB) temperature (example 170°C) during the shrink process resulted in increased resist thermal flow leading to worse shrink ID bias of 3.5 nm. As different pitch pattern has different proximity effect and matching with illumination condition, uneven dose is expected on them. These differences in dose required to obtain same through pitch (1:X, X-1, 1.5, 2, 3, 5) CD was assigned as the cause for shrink ID bias as the de-protection chemistry is related to dose which affects the shrink amount. This was further confirmed by flood exposure of after developed image (ADI) which reduced shrink ID bias from 3.5 nm to 1.8 nm. We concluded that the flood exposure makes the ADIs of the resist chemically uniform thereby minimizing shrink ID bias. Based on these studies, a mechanism for shrink ID bias is proposed. A modified NSM with 1.2 nm shrink ID bias has been developed without the need for the flood exposure.

Combinatorial process optimization for negative photo-imageable spin-on dielectrics and investigation of post-apply bake and post-exposure bake interactions

Patternable dielectric materials were developed and introduced to reduce semiconductor manufacturing complexity and cost of ownership (CoO). However, the bestowed dual functionalities of photo-imageable spin-on dielectrics (PSOD) put great challenges on the material design and development. In this work, we investigated the combinatorial process optimization for the negative-tone PSOD lithography by employing the Temperature Gradient Plate (TGP) technique which significantly reduced the numbers of wafers processed and minimized the developmental time. We demonstrated that this TGP combinatorial is very efficient at evaluating the effects and interactions of several independent variables such as post-apply bake (PAB) and post-exposure bake (PEB). Unlike most of the conventional photoresists, PAB turned out to have a great effect on the PSOD pattern profiles. Based on our extensive investigation, we observed great correlation between PAB and PEB processes. In this paper, we will discuss the variation of pattern profiles as a matrix of PAB and PEB and propose two possible cross-linking mechanisms for the PSOD materials to explain the unusual experimental results.

A phase segregating polymer blend for 2xnm feature applications

A phase segregating polymer blend comprising a SOD precursor polysilazane and an organic polymer PSαMS [poly(styrene-co-α-methyl styrene)] was studied. By utilizing similar approaches employed in DSA (directed self-assembly) such as patterned substrates, surface chemical modification etc and their combination, we achieved 2xnm spacer and airgap-like structure. Vertical phase separation and cylinder microdomains in the film of this blend can be straightforwardly observed by cross-section SEM (Scanning Electron Microscope) respectively. The airgap-like structure derived from cylinder microdomains was directly obtained on ArF resist pattern. Spacer derived from vertical phase separation was obtained on pretreated ArF resist pattern.

Photo-imageable spin-on dielectrics for TSV 3D packaging applications

Photo-imageable spin-on dielectrics (PSOD) with low dielectric constant were developed for TSV 3D packaging applications. Negative-tone PSOD with high resolution was devised to afford patterned dielectrics through simplified process, i.e. lithography and thermal annealing, in comparison to conventional CVD / Lithography / DRIE integration process. All processes employed in the PSOD fabrication are performed at low temperature (≤200°C) in order to meet the relatively low temperature constraints from conventional packaging materials.

Negative photo-imageable spin-on dielectrics: report on progress, challenges, and opportunities

From the perspectives of IC fabrication simplification, cost reduction, and waste material cutback, it is highly desirable to combine the traditional pattern formation step (lithographical processes) and the pattern transfer step (etch processes) into a single step. Photo-imageable spin-on dielectrics (PSOD) render it possible to achieve the aforementioned goal. However, the bestowed dual functionalities on PSOD put great challenges on the material design and development. PSOD needs not only to match all the performances of the advanced resists, but also to undertake all the duties of the dielectrics on the chips. We wish to report our modular approach employing Si-containing materials to address the challenge and to meet the requirements from the different material roles. This paper will also discuss the investigation and progress on lithographic performance, cure behaviors, thermal stability, and electrical and mechanical properties.