Yusuke Takano

Image Reversal Trilayer Process Using Standard Positive Photoresist

Conventional trilayer schemes alleviate the decreasing photoresist budgets as well as satisfy the antireflection issues associated with high NA imaging. However, a number of challenges still exist with standard trilayer processing, most notable among which is the lack of broad resist compatibility and trade-offs associated with improving Si content, such as stability and lithography performance. One way to circumvent these issues is to use a silicon hard mask coated over a photoresist image of reverse tone to the desired pattern. Feasibility of this image reversal trilayer process was demonstrated by patterning of trenches and contact holes in a carbon hard mask from line and pillar photoresist images, respectively. This paper describes the lithography, pattern transfer process and materials developed for the image reversal trilayer processing.

Newly developed RELACS materials and process for 65 nm nodes

We have developed a new ArF-RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) material called AZ-LExp.R720. The principle and process procedure of LExp.R720 are almost identical to those previously developed with KrF lithography. The extent of crosslinking reactions and the mobility balance of chemical components at the boundary between resist and the RELACS film is adjusted to ArF resist chemistry. LExp.R720 can vary shrinkage from 10 to 40nm by controlling the process conditions, mainly the mixing bake temperature. The amount of shrinkage is independent of pattern pitch and focus. We confirmed that pattern profile, lithography margin, CD uniformity, etching resistance, and pattern defects were not deteriorated by the RELACS process with deionized water development. L.ExpR720 was able to get an amount of shrinkage with several of ArF resists, which has commercial applications. In conclusion, we believe that LExp.R720 is extremely useful for 65 nm node and next generation devices.

Double imaging with resist freezing in a vapor reaction chamber

Cost-effective approaches to double patterning are currently an area of intense interest. This paper describes an update on the progress of AZs Vapor Reaction Chamber (VRC) freeze approach to double patterning. Swift integration of the VRC process will depend on whether or not a commercial prime chamber can function as a VRC chamber without modifications. Procedures for testing this were developed and applied to a lab VRC and 2 AHD modules. Results demonstrate that for the 8in ADH the across wafer freeze uniformity is within the experimental error of the FT-IR measurements used to evaluate the process, but that some slight variation was seen for the 12in ADH. In addition, progress has been made in improving double imaging profiles over earlier work which used the same resist in both exposures on ArF 1C5D substrates. This work looked at the benefits of using different substrates, establish a suitable resist for each exposure, and using substrate treatments to improve profiles.