Tatsushi Nakahara

Ultrafast optoelectronic packet processing for asynchronous,optical-packet-switched networks [Invited]

Feature Issue on Optical Interconnection Networks (OIN). We describe hybrid optical-electrical systems that perform header processing and buffering of ultrafast, asynchronous optical packets. Our systems are enabled by three key, novel devices: an all-optical serial-to-parallel converter, an optical clock-pulse generator, and a photonic parallel-to-serial-converter. These devices allow utilization of complementary metal-oxide semiconductor technology for compact, highly functional optical packet processing. A simplified node architecture for asynchronous, optical- packet-switched networks is made possible by these systems with all the necessary node functions integrated compactly. We also demonstrate an optical label swapper and a photonic random access memory for 40-Gbit/s, 16-bit, asynchronous optical packets.

Photonic random access memory for 40-Gb/s 16-b burst optical packets

We present a photonic random access memory (RAM) that can write and read high-speed asynchronous burst optical packets freely by specifying addresses. The photonic RAM consists of an optical clock-pulse generator, an all-optical serial-to-parallel converter, a photonic parallel-to-serial converter, all developed by us, and a complementary metal-oxide-semiconductor RAM as a storage medium, and features large capacity, long-term storage, random access at an arbitrary timing, low power consumption, and compactness. We experimentally confirm its basic operation for 40-Gb/s 16-b optical packets.

Monolithically integrated photonic switching device using an MSM PD, MESFETs, and a VCSEL

We have fabricated a photonic switching device that monolithically integrates a metal-semiconductor-metal photodetector, metal-semiconductor field-effect transistors, and a vertical-cavity surface-emitting laser. This device can perform both NOR- and OR-types of operation with thresholding input-output characteristics. The contrast ratio is more than 30 dB with optical gain. The device also shows a 3-dB bandwidth of 220 MHz and switching energy of 700 fJ at a 100-MHz frequency.<<ETX>>

40-Gbit/s label recognition and 1 /spl times/ 4 self-routing using self-serial-to-parallel conversion

Label recognition of 40-Gbit/s 16-bit burst-mode optical packets is demonstrated using an optical clock-pulse generator, an all-optical serial-to-parallel converter, and a CMOS electronics circuit. A compact 16-channel all-optical serial-to-parallel converter module was developed using a surface-emitting planar lightwave circuit and a spin-polarized surface-reflection all-optical switch made of low-temperature grown Be-doped strained InGaAs/InAlAs multiple quantum wells. 1 /spl times/ 4 self-routing is also demonstrated using two-channel control signals generated from the CMOS circuit according to a routing table.

Performance comparison between multiple-quantum-well modulator-based and vertical-cavity-surface-emitting laser-based smart pixels

We compared multiple-quantum-well modulator-based smart pixels and vertical-cavity-surface-emitting laser (VCSEL) based smart pixels in terms of optical switching power, switching speed, and electric-power consumption. Optoelectronic circuits integrating GaAs field-effect transistors are designed for smart pixels of both types under the condition that each pixel has an optical threshold and gain. It is shown that both types perform maximum throughput of ~3 Tbps/cm(2). In regard to design flexibility, the modulator type is advantageous because switching time can be reduced by supplying large electric power, whereas switching time and electric-power consumption are limited to larger than certain values in the VCSEL type. In contrast, in regard to optical implementation, the VCSEL type is advantageous because it does not need an external bias-light source, whereas the modulator type needs bias-light arrays that must be precisely located because the small modulator diameter, <10 µm, is essential to high-speed operation. A bias-light source that increases the total power consumption of the system may offset the advantages of the modulator type.

Torus-Topology Data Center Network Based on Optical Packet/Agile Circuit Switching with Intelligent Flow Management

We review our work on an intra-data center (DC) network based on co-deployment of optical packet switching (OPS) and optical circuit switching (OCS), conducted within the framework of a five-year-long national R&D program in Japan (~March 2016). For the starter, preceding works relevant to optical switching technologies in intra-DC networks are briefly reviewed. Next, we present the architecture of our torus-topology OPS and agile OCS intra-DC network, together with a new flow management concept, where instantaneous optical path on-demand, so-called Express Path is established. Then, our hybrid optoelectronic packet router (HOPR), which handles 100 Gbps (25 Gbps × 4-wavelength) optical packets and its enabling device and sub-system technologies are presented. The HOPR aims at a high energy-efficiency of 0.09 [W/Gbps] and low-latency of 100 ns regime. Next, we provide the contention resolution strategies in the OPS and agile OCS network and present the performance analysis with the simulation results. It is followed by the discussions on the power consumption of intra-DC networks. We compare the power consumption and the throughput of a conventional fat-tree topology with the N-dimensional torus topology. Finally, for further power saving, we propose a new scheme, which shuts off HOPR buffers according to the server operation status.

Design approaches for VCSEL’s and VCSEL-based smart pixels toward parallel optoelectronic processing systems

The technical issues involved in applying vertical-cavitysurface-emitting lasers (VCSELs) to parallel opticalinterconnection systems are discussed from the viewpoint of theirapplication to asynchronous transfer mode switching and parallelcomputer systems. We also discuss approaches to designing a VCSELarray structure for high-speed modulation and the effect ofpixel-performance homogeneity on the transmission bandwidth and powerconsumption. We review monolithic and hybrid integrationtechnologies for VCSEL-based smart-pixel arrays, and we estimate themaximum pixel number and input-output throughput allowed in a chip, considering the power consumption and pixel homogeneity. We showthat a one-chip optoelectronic parallel processing system comprisingmore than 1000 processor elements is possible when smart-pixel arraysare fabricated under the 0.25-mum complementary metal-oxide semiconductor design rule.

Novel technology for hybrid integration of photonic and electronic circuits

We have developed a new three-dimensional integration technology which involves hybrid integration of photonic and electronic circuits by means of polyimide bonding. To demonstrate this technology, we fabricated a GaAs metal-semiconductor-metal photodetector on a silicon substrate. Each photodetector on a polyimide layer is electrically connected to the electrode on the silicon substrate. The electrical interconnection between the photodetector and electrode on the silicon substrate consists of electroplated gold through a through-hole. The photoresponsivity of the photodetector is 0.3 A/W.

Optical single-clock-pulse generator using a photoconductive sample-and-hold circuit for processing ultrafast asynchronous optical packets

A scheme is proposed for generating a packet-level optical single-clock-pulse that uses an InP metal-semiconductor-metal photodiode-based sample-and-hold circuit and a gain-switched laser diode. A 3.3-ps single-pulse generation synchronized to the first bit pulse of an incoming ultrafast burst optical packet is demonstrated. The generated pulse has constant timing, intensity, and polarization; hence, it is suitable for use as the control pulse of an all-optical switching device used in a photonic packet-switched network node operating at over 40 Gbit/s.

Hybrid integration of smart pixels by using polyimide bonding: demonstration of a GaAs p-i-n photodiode/CMOS receiver

The fabrication procedure of smart pixels based on a hybrid integration of compound semiconductor photonic devices with silicon CMOS circuits is described. According to the 0.8-/spl mu/m design rule, CMOS receiver/transmitter circuits are designed for use in vertical-cavity surface-emitting laser (VCSEL)-based smart pixels, and 16/spl times/16 and 2/spl times/2 Banyan-switch smart-pixel chips are also designed. By using our polyimide bonding technique, we integrated GaAs pin-photodiodes hybridly on the CMOS circuits. The photodetector (PD)/CMOS hybrid receiver operated error free at up to 800 Mb/s. Successful optical/optical (O/O) operation (a bit rate up to 311 Mbit/s) of the 2/spl times/2 Banyan-switch smart-pixel chip implemented with another VCSEL chip is also demonstrated.