Salah Ibrahim

Simulation of Static Optical XPM in Active MMI Couplers

Based on the FD-BPM and including the distribution of photon density, carrier density, and refractive index, a simulation code is used to analyze the static performance of active MMI couplers in the presence of two different optical signals. To examine the feasibility of a novel all-optical switch based on active MMI; the code is mainly used to evaluate the amount of phase change resulting in the output of one optical signal by varying the intensity of the other at different injected carrier density.

A torus datacenter network based on OPS/OCS/VOCS enabled by smart flow management

We present an energy-efficient, low-latency, torus-topology intra-data center network with the deployment of 100-Gb/s hybrid optoelectronic routers, where OPS, OCS and virtual OCS are all supported on a single hardware platform enabled by smart flow management.

Torus data center network with smart flow control enabled by hybrid optoelectronic routers [Invited]

A torus-topology photonic data center network with smart flow control is presented, where optical packet switching (OPS), optical circuit switching (OCS), and virtual OCS (VOCS) schemes are all enabled on a unified hardware platform via the combination of hybrid optoelectronic routers (HOPR) and a centralized network controller. An upgraded HOPR is being developed with the goal of handling 100 Gbps optical packets with a high energy efficiency of 90 mW/Gbps and low latency of less than 100 ns. The architecture of HOPR and its enabling technologies are reviewed, including a label processor, optical switch, and optoelectronic shared buffer. We also explain the concept and operation mechanisms of both the data and control planes in the hybrid OPS/OCS/VOCS torus network. The performance of these three transmission modes is evaluated by numerical simulations for a network composed of 4096 HOPRs.

A novel optoelectronic serial-to-parallel converter for 25-Gbps burst-mode optical packets

A new optoelectronic serial-to-parallel converter (SPC) has been developed to interface 25-Gbps asynchronous optical packets to CMOS circuitry. Other than all previous optoelectronic SPCs that are limited to single-shot operation and hence that can only be used for packet label processing, the SPC presented here can operate repeatedly with a period of as low as 640 ps to perform 1:16 conversion for an entire burst-mode 25-Gbps optical packet. The new SPC adopts a shared-trigger configuration and hence a single device can either convert a single packet or dual packets simultaneously. In this paper, the design and operation of the new SPC is explained after reviewing the fundamentals of performing bit-by-bit serial-to-parallel conversion by using HEMT-arrays and MSM-PDs. The response of the fabricated SPC device is presented and explained, together with the experimental work done to demonstrate 1:16 dual packet conversion at 25 Gbps.

Low-Power Optical Packet Switching for 100-Gb/s Burst Optical Packets With a Label Processor and 8 × 8 Optical Switch

We demonstrate error-free 100-Gb/s optical packet switching with low power consumption by using a combination of a label processor and 8 × 8 broadcast-and-select (B&S) optical switch. To achieve energy-efficient label processing, an optical-trigger-pulse generator that consumes energy only for a very short duration is realized, whereas the optoelectronic serial-to-parallel converter used to interface the fast label bits to a slow CMOS processor has been improved to operate with a reduced trigger pulse energy of 0.35 pJ. Moreover, the electro-absorption-modulator-based B&S optical switch is significantly enhanced by introducing a surface ground electrode for eliminating electrical crosstalk and integrated spot-size converters with easy fabrication process. The total power consumption of the full 8 × 8 optical packet switch is estimated to be as low as 27.3 W or 3.4 W/100-Gb/s port.

Burst-mode optical label processor with ultralow power consumption

A novel label processor subsystem for 100-Gbps (25-Gbps × 4λs) burst-mode optical packets is developed, in which a highly energy-efficient method is pursued for extracting and interfacing the ultrafast packet-label to a CMOS-based processor where label recognition takes place. The method involves performing serial-to-parallel conversion for the label bits on a bit-by-bit basis by using an optoelectronic converter that is operated with a set of optical triggers generated in a burst-mode manner upon packet arrival. Here we present three key achievements that enabled a significant reduction in the total power consumption and latency of the whole subsystem; 1) based on a novel operation mechanism for providing amplification with bit-level selectivity, an optical trigger pulse generator, that consumes power for a very short duration upon packet arrival, is proposed and experimentally demonstrated, 2) the energy of optical triggers needed by the optoelectronic serial-to-parallel converter is reduced by utilizing a negative-polarity signal while employing an enhanced conversion scheme entitled the discharge-or-hold scheme, 3) the necessary optical trigger energy is further cut down by half by coupling the triggers through the chips backside, whereas a novel lens-free packaging method is developed to enable a low-cost alignment process that works with simple visual observation.

Hybrid Optoelectronic Router for Future Optical Packet‐ Switched Networks

With the growing demand for bandwidth and the need to support new services, several challenges are awaiting future photonic networks. In particular, the performance of cur‐ rent network nodes dominated by electrical routers/switches is seen as a bottleneck that is accentuated by the pressing demand for reducing the network power consumption. With the concept of performing more node functions with optics/optoelectronics, opti‐ cal packet switching (OPS) provides a promising solution. We have developed a hybrid optoelectronic router (HOPR) prototype that exhibits low power consumption and low latency together with high functionality. The router is enabled by key optical/optoelec‐ tronic devices and subsystem technologies that are combined with CMOS electronics in a novel architecture to leverage the strengths of both optics/optoelectronics and electron‐ ics. In this chapter, we review our recent HOPR prototype developed for realizing a new photonic intra data center (DC) network. After briefly explaining about the HOPR‐based DC network, we highlight the underlying technologies of the new prototype that enables label processing, switching, and buffering of asynchronous arbitrary‐length 100‐Gbps (25‐Gbps × 4λs) burst‐mode optical packets with enhanced power efficiency and reduced latency.

Hybrid OPS/OCS data center network with Torus Topology enabled by hybrid optoelectronic router

With the continuous growth of internet, mobile and cloud computing services, the network traffic in data centers (DCs) is drastically increasing. According to recent estimates 76% of this traffic exists within the DC itself; hence the DC network should be able to handle huge amounts of data while enabling connectivity of any server-to-server. In the traditional DC network, the widely deployed high-capacity switches/routers are resulting in high power consumption and high latency.

100-Gbps technologies of hybrid optoelectronic routers for a Torus datacenter network

We present the recent developments on the underlying 100-Gbps optical packet processing technologies for the hybrid optoelectronic router (HOPR) prototype being developed to enable an energy-efficient and low-latency Torus photonic data center network equipped with smart flow-control. In the new 100-Gbps HOPR upgraded from an earlier prototype, we target an energy consumption of 90 mW/Gbps and latency of less than 100 ns. Together with HOPRs architecture, we review the role of the newly developed subsystems namely the label processor, optical switch, and optoelectronic shared buffer in achieving the new targets.

Bypassing routes strategy for optical circuits in OPS-based data center networks

In OPS-based data center networks, setting up temporal OCS paths for high-reliability-required large data transmissions is preferred. However, inappropriate OCS path selection could severely affect the original OPS traffic, which is because OCS path may break the network topology and cause OPS packet circulations. We propose to hold bypassing routes for every link of the OCS path when it is established. Then, the OPS packets could bypass the OCS links by being deflected to the bypassing routes. Therefore, this method facilitates the coexistence of OCS in OPS-based data center networks. Simulations demonstrate the benefit achieved by our proposal compared to no-bypassing-route scenarios.