Tatsuya Onuki

A 3bit/cell nonvolatile memory with crystalline In-Ga-Zn-O TFT

A 3bit/cell nonvolatile oxide semiconductor RAM (NOSRAM) test die comprising c-axis aligned crystal In-Ga-Zn-O TFTs has been fabricated. The write time of the test die is 100 ns. The test die collectively reads multilevel data within 900 ns with a 3bit A/D converter serving as reading circuit. The endurance of the 3bit/cell NOSRAM cell is more than 1012 cycles.

DRAM Using Crystalline Oxide Semiconductor for Access Transistors and Not Requiring Refresh for More Than Ten Days

We fabricated a dynamic random access memory (DRAM) using crystalline oxide semiconductor (OS) transistors and not requiring refresh for more than ten days. We call this memory a dynamic oxide semiconductor random access memory (DOSRAM). A crystalline oxide semiconductor is an In-Ga-Zn-oxide (IGZO) semiconductor and has a c-axis aligned crystal (CAAC) structure. A crystalline OS transistor has extremely low off-state current. The DOSRAM uses this device for access transistors, and can have a very long refresh cycle. A memory cell array made of a crystalline OS layer can be stacked on peripheral circuits made of a silicon (Si) semiconductor layer; thus, the area of the DOSRAM can be decreased.

A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor

A flip-flop achieving high-speed backup utilizing a Si transistor and long-term retention with zero standby power by means of a transistor of c-axis aligned crystalline (CAAC) In-Ga-Zn oxide, a kind of CAAC oxide semiconductor, featuring extremely low off-state current is proposed. Using the flip-flop, a 32-bit processor has been fabricated with 350-nm Si/180-nm CAAC oxide semiconductor technology, and demonstrated data backup and power shutdown in 1.5 clock cycles at a low power of 1.77 nJ, data recovery in 2.5 clock cycles, and data retention with zero standby power for at least a day. According to simulation results, fast backup and long-term retention can also be achieved with 45-nm Si/180-nm CAAC oxide semiconductor technology.

Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating

A chip of embedded SRAM having backup circuits using a 60-nm c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as CAAC indium-gallium-zinc oxide (CAAC-IGZO) and Cortex-M0 core having flip-flops with CAAC-OS backup circuits is fabricated. The SRAM and M0 core can retain data using the backup circuits during power-off; thus, they can perform power gating (PG) with backup time of 100 ns and recovery time of 10 clock cycles (including data restoration time (100 ns)). Further, memory cell area and performance in combining a 45-nm Si SRAM memory cell with 60-nm CAAC-OS are estimated to have negligible overhead.

SRAM with c-axis aligned crystalline oxide semiconductor: Power leakage reduction technique for microprocessor caches

SRAM with backup circuits using a crystalline oxide semiconductor (OS) (e.g., a c-axis aligned crystalline oxide semiconductor (CAAC-OS) typified by CAAC In-Ga-Zn oxide (CAAC-IGZO)) is reported. Results of cell-level simulation based on 45-nm Si/100-nm OS process technology show backup time of 3.9 ns, recovery time of 2.0 ns, and break-even time of 21.7 ns. The OS-SRAM cell can replace a standard-SRAM cell without area overhead, which does not significantly affect normal operation. A 32-bit microprocessor test chip (350-nm Si/180-nm OS technology) with cache memory including the OS-SRAM was fabricated to demonstrate the intended normal and power-gating operations. The test chip demonstrated 97.6% standby power saving.

16.9 A 128kb 4b/cell nonvolatile memory with crystalline In-Ga-Zn oxide FET using V t , cancel write method

As the number of devices connected to the Internet increases, servers and mobile devices must process increasingly large volumes of data, and also accommodate the increasing demand for high-speed and large-capacity working memory keeping the power consumption low. This need is being fulfilled by emerging devices, such as resistive RAM, phase-change RAM, and MRAM [1], which realize high-speed, high-density and nonvolatile memory, significantly enhancing the performance of CPUs with integrated memories.

State retention flip flop architectures with different tradeoffs using crystalline indium gallium zinc oxide transistors implemented in a 32-bit normally-off microprocessor

As leakage power continues to increase when transistor sizes are downscaled, it becomes increasingly hard to achieve low power consumption in modern chips. Normally-off processors use state-retention and non-volatile circuits to make power gating more efficient with less static power. In this paper, we propose two novel state-retention flip-flop designs based on a parallel and series retention circuit architectures utilizing crystalline indium gallium zinc oxide transistors, which can achieve state retention with zero static power. To demonstrate the application of these different designs, they are implemented in a 32-bit normally-off microprocessor with an energy break-even time of 1.47 µs for the parallel type design and 0.93 µs for the series type design, at a clock frequency of 15 MHz. We show that decreasing the power supply duty cycle to 0.9%, the average current of the processor core can be decreased by over 99% using either type of flip-flop.

Fabrication of dynamic oxide semiconductor random access memory with 3.9 fF storage capacitance and greater than 1 h retention by using c-axis aligned crystalline oxide semiconductor transistor with L of 60 nm

A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.

Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium–Gallium–Zinc Oxide FET Integrated With 65-nm Si CMOS

Low-power embedded memory and an ARM Cortex-M0 core that operate at 30 MHz were fabricated in combination with a 60-nm c-axis aligned crystalline indium–gallium–zinc oxide FET and a 65-nm Si CMOS. The embedded memory adopted a structure wherein oxide semiconductor-based 1T1C cells are stacked on Si sense amplifiers. This memory achieved a standby power of 3 nW while retaining data and an active power of 11.7

Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS

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