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Dive into the research topics where Teck-Gyu Kang is active.

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Featured researches published by Teck-Gyu Kang.


electronic components and technology conference | 2001

Wide area vertical expansion (WAVE/sup TM/) package design for high speed application: reliability and performance

Young-Gon Kim; Ilyas Mohammed; Byong-Su Seol; Teck-Gyu Kang

A two metal flex-based WAVE package has been developed to replace four metal rigid based PBGA package. High board-level reliability was the primary motivation for this project and an equivalent electrical performance was a challenging target. All the package dimensions were maintained the same as the reference package to allow direct replacement. As a result of the one-year-long development program, the required reliability and performance goals were met successfully. This paper mainly describes the WAVE package design for reliability and performance. Optimal lead design is the most important step for reliable package development. The WAVE geometry model (WAVEGM) was developed to analyze the lead type, lead orientation, bump height, and injection lift height. The 2-metal flex tape was chosen to replace the original 4-metal rigid substrate due to its thinner dielectric layer, lower dielectric constant and improved trace/space design capability. The electrical performance was verified by both simulation and actual measurements of a test device.


electronic components and technology conference | 2008

Reliability of high-end flip-chip package with large 45nm ultra low-k die

Anurag Bansal; Teck-Gyu Kang; Yuan Li

The ultra low-K (ULK) dielectric material employed in 45 nm process technology is more porous and brittle than low-K dielectric used in prior generations. This paper looks into the effects of packaging materials on the reliability of a 42.5 times 42.5 mm flip-chip package assembled by a 20 times 20 mm ULK daisy chain die with 180 mum bump pitch and organic build-up thin-core substrate. Underfill materials with low Tg and high modulus, high Tg and high modulus, and high Tg and low modulus have been evaluated. In addition the effects of die thickness were studied. Finite element modeling, room temperature coplanarity, component-level and board-level temperature cycling tests have been used to study the different underfill materials and die thicknesses. Results show that room temperature warpage, propensity for ULK delamination, and solder joint reliability were significantly affected by the underfill properties.


Archive | 2005

Microelectronic packages and methods therefor

Belgacem Haba; Masud Beroz; Teck-Gyu Kang; Yoichi Kubota; Sridhar Krishnan; John B. Riley; Ilyas Mohammed


Archive | 2012

Package-on-package assembly with wire bonds to encapsulation surface

Hiroaki Sato; Teck-Gyu Kang; Belgacem Haba; Philip R. Osborn; Wei-Shun Wang; Ellis Chau; Ilyas Mohammed; Norihito Masuda; Kazuo Sakuma; Kiyoaki Hashimoto; Kurosawa Inetaro; Tomoyuki Kikuchi


Archive | 2005

Components with posts and pads

Yoichi Kubota; Teck-Gyu Kang; Jae M. Park; Belgacem Haba


Archive | 2007

Fine pitch microcontacts and method for forming thereof

Belgacem Haba; Yoichi Kubota; Teck-Gyu Kang; Jae M. Park


Archive | 2006

Substrate for a flexible microelectronic assembly and a method of fabricating thereof

Teck-Gyu Kang; Jae M. Park; Yoichi Kubota


Archive | 2012

Package on package configurations with embedded solder balls and interposal layer

Teck-Gyu Kang


Archive | 2011

Semiconductor chip assembly and method for making same

Teck-Gyu Kang; Wei-Shun Wang; Hiroaki Sato; Kiyoaki Hashimoto; Yoshikuni Nakadaira; Norihito Masuda; Belgacem Haba; Ilyas Mohammed; Philip Damberg


Archive | 2005

Electrical ground method for ball stack package

Philip R. Osborn; Teck-Gyu Kang; Ilyas Mohammed

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