Ilyas Mohammed

Wide area vertical expansion (WAVE/sup TM/) package design for high speed application: reliability and performance

A two metal flex-based WAVE package has been developed to replace four metal rigid based PBGA package. High board-level reliability was the primary motivation for this project and an equivalent electrical performance was a challenging target. All the package dimensions were maintained the same as the reference package to allow direct replacement. As a result of the one-year-long development program, the required reliability and performance goals were met successfully. This paper mainly describes the WAVE package design for reliability and performance. Optimal lead design is the most important step for reliable package development. The WAVE geometry model (WAVEGM) was developed to analyze the lead type, lead orientation, bump height, and injection lift height. The 2-metal flex tape was chosen to replace the original 4-metal rigid substrate due to its thinner dielectric layer, lower dielectric constant and improved trace/space design capability. The electrical performance was verified by both simulation and actual measurements of a test device.

Thermal performance characteristics of folded stacked packages

The trend towards miniaturization and increased functionality has pushed for packaging more than one die together, while maintaining chip scale. Multi-chip packages consist of either vertical stacking of the die to reduce package footprint and/or placing dies adjacent to each other to improve functionality. The challenge lies in continuing to reduce the size while satisfying the stringent thermal, mechanical and electrical requirements of the wireless industry. One such solution in this area is the folded stacked technology developed by Tessera Technologies. In this design, the dies are placed side-by-side onto a substrate, which is then folded appropriately to obtain a low profile multi-chip CSP package. Their design allows the flexibility of different die sizes and die pad configurations to cater to different applications. Any multi-chip solution carries along with it the concern over its capability to dissipate heat quickly and effectively to prevent overheating of the die. Thus this work focuses on studying the thermal performance characteristics of a multi-die folded stack package.

A design and performance study of 3D packaging for high performance memory applications

To address the performance and miniaturization challenges being faced by the packaging industry, a novel packaging methodology is presented in this paper. A 3D packaging methodology that leverages the existing CSP (Chip Scale Packaging) infrastructure to design and build memory solutions that is high performing and highly dense is presented. The design includes the individual device package design, the 3D package design and module design. Both the electrical and thermal performance is optimized by modifying the three levels of design. The design trade-offs are studied in terms of performance and compared to the performance of single device packages. The 3D packages are analyzed electrically and thermally using finite element and finite difference-based commercial software. The electrical performance results are presented at a single device level and at the 3D package level. The thermal performance is determined under standard test conditions and actual operating environments. Finally, to illustrate the 3D packaging technique, a compact memory module is presented that offers high performance, has a low profile and enables dense memory systems.

Thermal Management of High Density Very Low Profile Memory Module

Thermal analysis is conducted on high density memory modules with 4 stack DDR2 package. Two interconnect technologies, ball stack and micro contact, are compared. Due to the high power density and limited space, thermal management of the modules is challenging. Limitation of conventional air cooling is discussed, and innovative cooling schemes are demonstrated.