Ted Taylor

Light sources for high-volume manufacturing EUV lithography: technology, performance, and power scaling

Abstract Extreme ultraviolet (EUV) lithography is expected to succeed in 193-nm immersion multi-patterning technology for sub-10-nm critical layer patterning. In order to be successful, EUV lithography has to demonstrate that it can satisfy the industry requirements in the following critical areas: power, dose stability, etendue, spectral content, and lifetime. Currently, development of second-generation laser-produced plasma (LPP) light sources for the ASML’s NXE:3300B EUV scanner is complete, and first units are installed and operational at chipmaker customers. We describe different aspects and performance characteristics of the sources, dose stability results, power scaling, and availability data for EUV sources and also report new development results.

Advancements in predictive plasma formation modeling

We present highlights from plasma simulations performed in collaboration with Lawrence Livermore National Labs. This modeling is performed to advance the rate of learning about optimal EUV generation for laser produced plasmas and to provide insights where experimental results are not currently available. The goal is to identify key physical processes necessary for an accurate and predictive model capable of simulating a wide range of conditions. This modeling will help to drive source performance scaling in support of the EUV Lithography roadmap. The model simulates pre-pulse laser interaction with the tin droplet and follows the droplet expansion into the main pulse target zone. Next, the interaction of the expanded droplet with the main laser pulse is simulated. We demonstrate the predictive nature of the code and provide comparison with experimental results.

Product and tool control using integrated auto macro defect inspection in the photolithography cluster

Defectivity control continues to challenge advanced semiconductor manufacturing, especially immersion lithography processes. Immersion exposure tools are sensitive to incoming wafer defects, including top coat voids, surface defects, and other random or systematic anomalies. A single defective wafer could contaminate the exposure tools immersion hood resulting in lengthy and costly repairs. To mitigate this problem, TEL developed an integrated and real-time macro inspection solution to identify defective wafers which could potentially damage immersion exposure tools. The Wafer Intelligent Scanner (WIS) module integrates within the CLEAN TRACKTM LITHIUS ProTM platform without impacting footprint or throughput. By utilizing user defined inspection criteria, wafers can be inspected prior to and after exposure for macro defects. Wafers failing to meet inspection criteria prior to exposure are automatically re-routed to bypass the exposure tool and subsequent process modules.

Investigation of optimized wafer sampling with multiple integrated metrology modules within photolithography equipment

Micron Technology, Inc., explores the challenges of defining specific wafer sampling scenarios for users of multiple integrated metrology modules within a Tokyo Electron Limited (TEL) CLEAN TRACKTM LITHIUSTM. With the introduction of integrated metrology (IM) into the photolithography coater/developer, users are faced with the challenge of determining what type of data is required to collect to adequately monitor the photolithography tools and the manufacturing process. Photolithography coaters/developers have a metrology block that is capable of integrating three metrology modules into the standard wafer flow. Taking into account the complexity of multiple metrology modules and varying across-wafer sampling plans per metrology module, users must optimize the module wafer sampling to obtain their desired goals. Users must also understand the complexity of the coater/developer handling systems to deliver wafers to each module. Coater/developer systems typically process wafers sequentially through each module to ensure consistent processing. In these systems, the first wafer must process through a module before the next wafer can process through a module, and the first wafer must return to the cassette before the second wafer can return to the cassette. IM modules within this type of system can reduce throughput and limit flexible wafer selections. Finally, users must have the ability to select specific wafer samplings for each IM module. This case study explores how to optimize wafer sampling plans and how to identify limitations with the complexity of multiple integrated modules to ensure maximum metrology throughput without impact to the productivity of processing wafers through the photolithography cell (litho cell).

Effect of Ceria Particle-Size Distribution and Pressure Interactions in Chemo-Mechanical Polishing (CMP) of Dielectric Materials

Effect of ceria particle-size distribution and pressure interactions in CMP of dielectric materials and the subsequent surface generation mechanisms is investigated in detail. The removal rate is observed to correlate primarily with the slurry mean particle-size distribution (D50) and reach early rate saturation with decreasing particle size. Slurries with tighter particlesize distribution exhibit a logarithmic relationship with pressure, while a linear relationship is observed for wider distribution slurries. In contrast to the removal rate, surface roughness and degree of microscratches depend primarily on the tail distribution (D99) and increase with increasing particle size. The addition of a selective component to the slurry increases the rate differential between the slurries.