Tedi Kujofsa

Design of S-Graded Buffer Layers for Metamorphic ZnSySe1−y/GaAs (001) Semiconductor Devices

We present design equations for error function (or “S-graded”) graded buffers for use in accommodating lattice mismatch of heteroepitaxial semiconductor devices. In an S-graded metamorphic buffer layer the composition and lattice mismatch profiles follow a normal cumulative distribution function. Minimum-energy calculations suggest that the S-graded profile may be beneficial for control of defect densities in lattice-mismatched devices because they have several characteristics which enhance the mobility and glide velocities of dislocations, thereby promoting long misfit segments with relatively few threading arms. First, there is a misfit-dislocation-free zone (MDFZ) adjacent to the interface, which avoids dislocation pinning defects associated with substrate defects. Second, there is another MDFZ near the surface, which reduces pinning interactions near the device layer which will be grown on top. Third, there is a large built-in strain in the top MDFZ, which enhances the glide of dislocations to sweep out threading arms. In this paper we present approximate design equations for the widths of the MDFZs, the built-in strain, and the peak misfit dislocation density for a general S-graded semiconductor with diamond or zincblende crystal structure and (001) orientation, and show that these design equations are in fair agreement with detailed numerical energy-minimization calculations for ZnSySe1−y/GaAs (001) heterostructures.

Equilibrium strain and dislocation density in exponentially graded Si1−xGex/Si (001)

We have calculated the equilibrium strain and misfit dislocation density profiles for heteroepitaxial Si1−xGex/Si (001) with convex exponential grading of composition. A graded layer of this type exhibits two regions free from misfit dislocations, one near the interface of thickness y1 and another near the free surface of thickness h−yd, where h is the layer thickness. The intermediate region contains an exponentially tapered density of misfit dislocations. We report approximate analytical models for the strain and dislocation density profile in exponentially graded Si1−xGex/Si (001) which may be used to calculate the effective stress and rate of lattice relaxation. The results of this work are readily extended to other semiconductor material systems and may be applied to the design of exponentially graded buffer layers for metamorphic device structures including transistors and light emitting diodes.

Relaxation Dynamics and Threading Dislocations in ZnSe and ZnS y Se1−y /GaAs (001) Heterostructures

The design of lattice-mismatched semiconductor devices requires a predictive model for strains and threading dislocation densities. Previous work enabled modeling of uniform layers but not the threading dislocations in device structures with arbitrary compositional grading. In this work we present a kinetic model for lattice relaxation which includes misfit–threading dislocation interactions, which have not been considered in previous annihilation–coalescence models. Inclusion of these dislocation interactions makes the kinetic model applicable to compositionally graded structures, and we have applied it to ZnSe/GaAs (001) and ZnSySe1−y/GaAs (001) heterostructures. The results of the kinetic model are consistent with the observed threading dislocation behavior in ZnSe/GaAs (001) uniform layers, and for graded ZnSySe1−y/GaAs (001) heterostructures the kinetic model predicts that the threading dislocation density may be reduced by the inclusion of grading buffer layers employing compositional overshoot. This “dislocation compensation” effect is consistent with our high-resolution x-ray diffraction experimental results for graded ZnSySe1−y/GaAs (001) structures grown by photoassisted metalorganic vapor-phase epitaxy.

Initial misfit dislocations in a graded heteroepitaxial layer

We show that for a mismatched heteroepitaxial layer with linear compositional grading, the first misfit dislocations will be introduced at a finite distance yC from the substrate interface. This is of practical as well as fundamental importance; it alters the value of the critical layer thickness for lattice relaxation and it moves the misfit dislocations away from the interface, where contaminants and defects may cause dislocation pinning or mobility reduction. We have calculated the position of the initial misfit dislocations yC for linearly graded Si1−xGex/Si(001) heteroepitaxial layers with lattice mismatch given by f=Cfy, where Cf is the grading coefficient and y is the distance from the interface. The distance of the first misfit dislocations from the interface yC decreases with increasing grading coefficient but can exceed 40 nm in layers with shallow grading (|Cf|<12 cm−1). For the range of grading coefficients investigated, yC varies from 6% to 11% of the critical layer thickness. Based on the mo...

Evolution of Kinetically Limited Lattice Relaxation and Threading Dislocations in Temperature-Graded ZnSe/GaAs (001) Metamorphic Heterostructures

We have investigated the evolution of strain and threading dislocation density in metamorphic temperature-graded ZnSe buffer layers. Mismatched semiconductor heterostructures may be designed to take advantage of temperature grading to allow control over the relaxation process. To study temperature grading, we have applied a plastic flow model which predicts nonequilibrium strain relaxation as well as misfit and threading dislocation densities by accounting for the time evolution of kinetically limited and equilibrium strain relaxation, thermal activation of glide, and misfit–threading dislocation interactions. We considered ZnSe/GaAs (001) heterostructures comprising a convex-down (type A), linear (type B), and convex-up (type C) temperature grading profile. The thermal budget available for relaxation in these types of structures is controlled by the temperature grading profile, which consists of combinations of linear ramp-down and/or constant temperature growth; the temperature is varied from T0 (400°C to 600°C) at the substrate interface to TF = 300°C at the surface. We show that structures with a higher thermal budget exhibit a greater extent of relaxation (lower strains). At lower thicknesses, the dislocation density is dominated by the extent of relaxation, whereas at greater thicknesses, it is controlled by annihilation and coalescence mechanisms.

Electric circuit model for strained-layer epitaxy

For the design and analysis of a strained-layer semiconductor device structure, the equilibrium strain profile may be determined numerically by energy minimization but this method is computationally intense and non-intuitive. Here we present an electric circuit model approach for the equilibrium analysis of an epitaxial stack, in which each sublayer may be represented by an analogous configuration involving a current source, a resistor, a voltage source, and an ideal diode. The resulting node voltages in the analogous electric circuit correspond to the equilibrium strains in the original epitaxial structure. This new approach enables analysis using widely accessible circuit simulators, and an intuitive understanding of electric circuits may be translated to the relaxation of strained-layer structures. In this paper, we describe the mathematical foundation of the electrical circuit model and demonstrate its application to epitaxial layers of Si1−x Ge x grown on a Si (001) substrate.

Lattice relaxation and misfit dislocations in nonlinearly graded InxGa1 − xAs/GaAs (001) and GaAs1 − yPy/GaAs (001) metamorphic buffer layers

Recent results have shown that nonlinearly graded buffer layers may be beneficial for the reduction of threading dislocation densities in metamorphic semiconductor devices. In this work, the authors have studied the equilibrium strain relaxation and misfit dislocation densities in nonlinearly graded heterostructures with logarithmic grading, and compare the cases of InxGa1−xAs/GaAs and GaAs1−yPy/GaAs buffer layers. The authors show that differences in the elastic stiffness constants give rise to significantly different behavior in these two commonly used buffer layer systems. Moreover, the width of the dislocated region, the average misfit dislocation density, and surface in-plane strain may be related to the nonlinearity coefficient of the grading profile.

Equilibrium Lattice Relaxation and Misfit Dislocations in Step-Graded InxGa1−xAs/GaAs (001) and InxAl1−xAs/GaAs (001) Metamorphic Buffer Layers

The inclusion of metamorphic buffer layers (MBLs) in the design of lattice-mismatched semiconductor heterostructures is important in enhancing reliability and performance of optoelectronic and electronic devices through proper control of threading dislocations; threading dislocation can be reduced by allowing the distribution of the misfit dislocations throughout the MBL, rather than concentrating them at the interface where substrate defects and tangling can pin dislocations or otherwise reduce their mobility. Compositionally graded layers have been particularly used for this purpose and in this work we considered heterostructures involving a step-graded InxGa1−xAs or InxAl1−xAs epitaxial layer on a GaAs (001) substrate. For each structure type, we present minimum energy calculations including (i) the surface and (ii) average in-plane strain and (iii) the misfit dislocation density profile with various grading coefficients (thickness and indium composition variation). In both types of structures, the average in-plane strain and misfit dislocation density profile scale with the average grading coefficient, but InxAl1−xAs structures with a greater average elastic stiffness constants exhibit slightly higher average compressive in-plane strain (absolute valued) which is associated with higher misfit dislocation densities. However, the rate of change in the normalized relaxation percentage per unit thickness of each step with respect to the lattice mismatch of the step is lower in the InxAl1−xAs material system. The difference of the in-plane strain is small (<3%), however, so that these material systems are virtually interchangeable in terms of their mechanical behavior (<5.1% change in elastic constants).

Comparison of Continuously- and Step-Graded ZnSySe1−y/GaAs (001) Metamorphic Buffer Layers

The design of metamorphic buffer layers for semiconductor devices with reduced defect densities requires control of lattice relaxation and dislocation dynamics. Graded layers are beneficial for the design of these buffers because they reduce the threading dislocation density by (1) allowing the distribution of the misfit dislocations throughout the buffer layer therefore reducing pinning interactions, and (2) enhancing mobility from the high built-in surface strain which helps to sweep out threading arms. In this work, we considered heterostructures involving a linearly-graded (type A) or step-graded (type B) buffer grown on a GaAs (001) substrate. For each structure type, we studied the equilibrium configuration and the kinetically-limited lattice relaxation and non-equilibrium threading dislocations by utilizing a dislocation dynamics model. In this work, we have also considered heterostructures involving a constant composition ZnSySe1−y device layer grown on top of a GaAs (001) substrate with an intermediate buffer layer of linearly-graded (type C) or step-graded (type D) ZnSySe1−y. For each structure type, we studied the requirements on the thickness and compositional profile in the buffer layer for the elimination of all mobile threading dislocations from the device layer by the dislocation compensation mechanism.

Apparent critical layer thickness in ZnSe/GaAs (001) heterostructures and the role of finite experimental resolution

The critical layer thickness hc for the onset of lattice relaxation has important implications for the design of pseudomorphic and metamorphic II–VI device structures on lattice-mismatched substrates. Several theoretical models have been developed for the critical layer thickness, including the well-known force-balance model of Matthews and Blakeslee [J. Cryst. Growth 27, 188 (1974)]. Experimentally measured critical layer thicknesses in ZnSe/GaAs (001) heterostructures are often at variance with one another as well as the Matthews and Blakeslee model. By assuming that the lattice relaxation is a fixed fraction of the equilibrium relaxation (constant γ/γeq), Fritz [Appl. Phys. Lett. 51, 1080 (1987)] has shown that the measured hc may be much larger than the equilibrium value when using a finite experimental resolution. However, the assumption of constant fractional relaxation is not applicable to any heterostructure exhibiting kinetically limited lattice relaxation. In order to reconcile the conflicting r...