E. Suarez

Misfit dislocation density and strain relaxation in graded semiconductor heterostructures with arbitrary composition profiles

We present a computational approach for the determination of the equilibrium misfit dislocation density and strain in a semiconductor heterostructure with an arbitrary compositional profile. We demonstrate that there is good agreement between our computed results and known analytical solutions for heterostructures containing a single linearly graded layer or a single uniform composition layer. We have calculated the dislocation density and strain profiles in Si1−xGex/Si(001), InxGa1−xAs/GaAs(001), and ZnSySe1−y/GaAs(001) heterostructures, each containing a uniform composition layer (uniform layer) on a linearly graded buffer layer (graded layer). The density of misfit dislocations in the graded layer is inversely proportional to its grading coefficient and is unchanged by the presence of the uniform layer, but the dislocated thickness increases with the uniform layer thickness. If the uniform layer is sufficiently thick, misfit dislocations will exist throughout the graded layer, but additional misfit dis...

X-ray characterization of dislocation density asymmetries in heteroepitaxial semiconductors

We demonstrate an x-ray rocking curve method which allows detection of an asymmetry in the dislocation densities in an heteroepitaxial (001) zinc blende semiconductor layer. These dislocations exist on two types of slip systems with their misfit dislocation line segments oriented along either a [1−10] direction (type A) or a [110] direction (type B). An imbalance in the densities of dislocations on these slip systems produces an observable azimuthal variation in the rocking curve width for symmetric x-ray reflections. An approximate quantitative model allows the estimation of the dislocation densities on the two types of slip systems.

Annealing induced nanostructure and photoluminescence property evolution in solution-processed Mg-alloyed ZnO nanowires

Solution-processed Mg-alloyed ZnO nanowire arrays have been achieved recently without using high temperature annealing process. By introducing thermal annealing processes in oxygen-rich ambient condition, the UV near-band-edge (NBE) emission was surprisingly mitigated until disappeared with annealing temperature increasing from 400 to 900 °C. As the annealing temperature increased, intensity of UV peak decreased while intensity of visible peak (490–520 nm) increased. The structure evolution upon thermal annealing was revealed to be responsible for these abnormal photoluminescence property variations, where unusual (Zn,Mg)1.7SiO4 epitaxially evolved on ZnMgO nanowires surface and contributed to the quenching of UV NBE emission. The structure evolution induced UV-NBE quenching and nanoscale localized alloying in semiconductor ZnMgO nanowires could bring up opportunities in catalysis, optoelectronics, spintronics, and sensors.

Design of S-Graded Buffer Layers for Metamorphic ZnSySe1−y/GaAs (001) Semiconductor Devices

We present design equations for error function (or “S-graded”) graded buffers for use in accommodating lattice mismatch of heteroepitaxial semiconductor devices. In an S-graded metamorphic buffer layer the composition and lattice mismatch profiles follow a normal cumulative distribution function. Minimum-energy calculations suggest that the S-graded profile may be beneficial for control of defect densities in lattice-mismatched devices because they have several characteristics which enhance the mobility and glide velocities of dislocations, thereby promoting long misfit segments with relatively few threading arms. First, there is a misfit-dislocation-free zone (MDFZ) adjacent to the interface, which avoids dislocation pinning defects associated with substrate defects. Second, there is another MDFZ near the surface, which reduces pinning interactions near the device layer which will be grown on top. Third, there is a large built-in strain in the top MDFZ, which enhances the glide of dislocations to sweep out threading arms. In this paper we present approximate design equations for the widths of the MDFZs, the built-in strain, and the peak misfit dislocation density for a general S-graded semiconductor with diamond or zincblende crystal structure and (001) orientation, and show that these design equations are in fair agreement with detailed numerical energy-minimization calculations for ZnSySe1−y/GaAs (001) heterostructures.

Equilibrium strain and dislocation density in exponentially graded Si1−xGex/Si (001)

We have calculated the equilibrium strain and misfit dislocation density profiles for heteroepitaxial Si1−xGex/Si (001) with convex exponential grading of composition. A graded layer of this type exhibits two regions free from misfit dislocations, one near the interface of thickness y1 and another near the free surface of thickness h−yd, where h is the layer thickness. The intermediate region contains an exponentially tapered density of misfit dislocations. We report approximate analytical models for the strain and dislocation density profile in exponentially graded Si1−xGex/Si (001) which may be used to calculate the effective stress and rate of lattice relaxation. The results of this work are readily extended to other semiconductor material systems and may be applied to the design of exponentially graded buffer layers for metamorphic device structures including transistors and light emitting diodes.

Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeOx)-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.

Dislocations and strain relief in reverse-graded semiconductor layers

We have calculated the equilibrium misfit dislocation density and strain profiles in reverse-graded heteroepitaxial layers, using Si1?xGex/Si (0?0?1) as a model material system. In these structures there is a finite lattice mismatch at the substrate interface and the composition is graded linearly in such a way that the lattice mismatch decreases with distance from this interface. Reverse-graded layers exhibit two distinct behaviors which may be referred to as unkinked and kinked. In the unkinked reverse-graded layer the misfit dislocations are confined to a thin region near the substrate interface, the residual strain is a linear function of distance from the interface and the strain exhibits a sign reversal within the layer. Kinked reverse-graded layers exhibit a kink in the strain versus distance characteristic, and this kinked region contains a nearly constant density of misfit dislocations. We have developed models for the behavior of both types of reverse-graded layers, and we show that these models provide accurate predictions for Si1?xGex/Si (0?0?1) reverse-graded layers.

Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers

Three-state behavior has been demonstrated in Si and InGaAs field-effect transistors (FETs) when two layers of cladded quantum dots (QDs), such as SiOx-cladded Si or GeOx-cladded Ge, are assembled on the thin tunnel gate insulator. This paper describes FET structures that have the potential to exhibit four states. These structures include: (1) quantum dot gate (QDG) FETs with dissimilar dot layers, (2) quantum dot channel (QDC) with and without QDG layers, (3) spatial wavefunction switched (SWS) FETs with multiple coupled quantum well channels, and (4) hybrid SWS–QDC structures having multiple drains/sources. Four-state FETs enable compact low-power novel multivalued logic and two-bit memory architectures. Furthermore, we show that the performance of these FETs can be enhanced by the incorporation of II–VI nearly lattice-matched layers in place of gate oxides and quantum well/dot barriers or claddings. Lattice-matched high-energy gap layers cause reduction in interface state density and control of threshold voltage variability, while providing a higher dielectric constant than SiO2. Simulations involving self-consistent solutions of the Poisson and Schrödinger equations, and transfer probability rate from channel (well or dot layer) to gate (QD layer) are used to design sub-12-nm FETs, which will aid the design of multibit logic and memory cells.

Relaxation Dynamics and Threading Dislocations in ZnSe and ZnS y Se1−y /GaAs (001) Heterostructures

The design of lattice-mismatched semiconductor devices requires a predictive model for strains and threading dislocation densities. Previous work enabled modeling of uniform layers but not the threading dislocations in device structures with arbitrary compositional grading. In this work we present a kinetic model for lattice relaxation which includes misfit–threading dislocation interactions, which have not been considered in previous annihilation–coalescence models. Inclusion of these dislocation interactions makes the kinetic model applicable to compositionally graded structures, and we have applied it to ZnSe/GaAs (001) and ZnSySe1−y/GaAs (001) heterostructures. The results of the kinetic model are consistent with the observed threading dislocation behavior in ZnSe/GaAs (001) uniform layers, and for graded ZnSySe1−y/GaAs (001) heterostructures the kinetic model predicts that the threading dislocation density may be reduced by the inclusion of grading buffer layers employing compositional overshoot. This “dislocation compensation” effect is consistent with our high-resolution x-ray diffraction experimental results for graded ZnSySe1−y/GaAs (001) structures grown by photoassisted metalorganic vapor-phase epitaxy.

Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators

Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiOx-cladded Si or GeOx-cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiOx-cladded Si and GeOx-cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO2 tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (ID–VG) shows four-state behavior with two intermediate states between the conventional ON and OFF states.