Teh-Hua Ju

Thermosonic bonding of an optical transceiver based on an 8/spl times/8 vertical cavity surface emitting laser array

This paper reports the results of our thermosonic (T/S) flip-chip bonding process development for the assembly of a smart pixel array (SPA) using an 8/spl times/8 vertical cavity surface emitting laser (VCSEL) array. The introduction of ultrasonic energy into the flip-chip bonding process increases the speed of the assembly process while at the same time lowering the physical stresses (temperature and assembly force) applied to bond the components. Many empirical studies have shown that T/S flip-chip bonding is feasible, but there is a lack of detailed understanding of the effects of the ultrasonic energy on the bonding results. We are conducting experiments and developing models that will provide a sound understanding and a rational basis for T/S flip-chip bonding. In particular, we have addressed the problems of the impact of joint bump size, control of the assembly force, and the repeatability of the ultrasonic power. This report details our findings concerning the following aspects important to the development of T/S flip-chip bonding technology: (1) Computer modeling to guide the selection of design parameters and provide a basis to study the effects of the interaction of the critical design and process parameters on process yield. (2) Design of a new end effector for accurately applying and monitoring small assembly force. (3) Monitoring and controlling the impedance of the ultrasonic mechanical and electrical system in order to insure repeatable delivery of acoustic energy to the assembly.

Packaging of a 128 by 128 liquid-crystal-on-silicon spatial light modulator using self-pulling soldering

A self-pulling soldering technology has been demonstrated for assembling liquid crystal on silicon (LCOS) spatial light modulators (SLMs). Solder joints with different profiles and sizes are designed to provide vertical surface tension forces to control the gap accommodating the ferroelectric liquid crystal (FLC) layer in the range of a micron with sub-micron uniformity. This technology provides an automatic, batch assembly process for a LCOS SLM through one reflow process. The component designs and process optimization are described, and the first operational results are presented.<<ETX>>

Effects of Ceramic Ball-Grid-Array Package's Manufacturing Variations on Solder Joint Reliability

The effects of manufacturing variations on the reliability of solder joints between a ceramic ball grid array (BGA) package and a printed wiring board (PWB) are investigated. Three manufacturing parameters tinder consideration are 1) solder volume, 2) solder height, and 3) solder pad size. To study the manufacturing effects, a solder joint profile model is derived. Then the maximum strain is calculated, and the fatigue life of the solder joint is predicted. The accuracy of the solder profile model is verified by comparing its predicted profiles with experimental results. The fatigue life of a solder joint is estimated by the Coffin-Mansons relation. The calculations show that the manufacturing variations change the joint profile, and subsequently affect the fatigue life. The solder joints formed may have convex, cylindrical and concave profiles. The concave solder joints are preferred, which have long fatigue lives and are less sensitive to the manufacturing variations. For the convex solder joints, their fatigue lives are strongly affected by the joint height variation and by the combined effects of solder volume and pad size.

Thermosonic bonding: an alternative to area-array solder connections

Thermosonic bondings for flip-chip, TAB, or surface mount technologies are potential alternatives to solder connections. They are dry processes having low-cost, simplicity, and fine-pitch advantages. The applications of these new connection technologies are expected to grow if their two major problems, assembly yield and reliability, are solved. The assembly problem is studied in this paper. It is well known that the use of ultrasonic energy can significantly simplify metal bonding processes. However, the changes of thermosonic process windows for area-array connections are not controllable; the progress of this technology development is not encouraging. Using flip-chip bonding cases with 30- and 1000-I/O chips, this work studies the effects on yields from tool configurations and masses. The yield is closely related to the ultrasonic amplitude of metal bumps. The amplitude associated with a good bonding process for a 30-I/O chip is about 1.30 /spl mu/m. However, it could be reduced to 0.26 /spl mu/m when the die collet is enlarged for a 1000-I/O chip. Fortunately, such a reduction can be overcome by a design that changes the mass of the collet and the length of the shank. This paper will address the understanding and the control of these effects with experimental and modeling studies.<<ETX>>

Thermosonic flip-chip bonding for an 8/spl times/8 VCSEL array

The introduction of ultrasonic energy to the flip-chip bonding process has the potential to increase the speed of the operation while at the same time lowering the physical stresses on the bonded components. This is a significant consideration for the optoelectronics components that will be used in many single and multi-chip module assemblies. However, at this time, while many empirical studies have shown that thermosonic flip-chip bonding is feasible, there is a lack of detailed understanding of the effects of the ultrasonic energy on the bonding results. At the University of Colorado, we are conducting experiments and developing models that will provide a sound understanding and a rational basis for thermosonic flip-chip bonding. This report details our findings concerning the aspects important to the development of thermosonic flip-chip bonding technology.

Cost, performance, and reliability simulator for optical transceiver modules

The program couple combines simulators for optical performance, mechanical reliability, and production cost under a graphical-user interface to design, simulate, and evaluate micro-optomechanical structures. The thermal simulator predicts the package temperature distribution on the basis of the materials and the geometry as well as on heat sources, sinks, and boundary conditions. The thermal distribution is input to the mechanical simulator, which calculates the stresses or strains and displacements caused by differential thermal expansion. The optical simulator predicts the impact on the optical efficiency and the cross talk of mechanical and optical parameter variations such as solder heights, misalignments, and wavelength distributions. The cost simulator represents the manufacturing process flow and calculates the final cost and the cost sensitivity on basis of the cost and the yield of each process step. By means of balancing detector and coupling yield, cosimulation from optical to cost domains determines the optimum detector size to produce the lowest-cost transceiver module.

Couple: an integrated model for optical interconnect modules

We have developed a modeling tool that integrates optical, cost, thermal, mechanical, and solder models under a common user interface. The models are connected together to allow trade-off studies between parameters existing within different models. We have applied the integrated models to a family of optical interconnect modules. In this paper we will show how the integrated models can help the users design, as well as understand tradeoffs, in optical modules.

Packaging of ferroelectric liquid crystal-on-silicon spatial light modulators

A self-pulling soldering technology has been demonstrated for assembling liquid crystal on silicon (LCOS) spatial light modulators (SLMs). One of the major challenges in manufacturing the LCOS modules is to reproducibly control the thickness of the gap between the very large scale integrated circuit (VLSI) chip and the cover glass. The liquid crystal material is sandwiched between the VLSI chop and the cover glass which is coated with a transparent conductor. Solder joints with different profiles and sizes have been designed to provide surface tension forces to control the gap accommodating the ferroelectric liquid crystal layer in the range of a micron level with sub- micron uniformity. The optimum solder joint design is defined as a joint that results in the maximum pulling force. This technology provides an automatic, batch assembly process for a LCOS SLM through one reflow process. Fluxless soldering technology is used to assemble the module. This approach avoids residues from chemical of flux and oxides, and eliminates potential contamination to the device. Two different LCOS SLM designs and the process optimization are described.

Packaging Of Liquid Crystal On Silicon Modulators Using Solder

A liquid crystal on metallized silicon modulator is demonstrated by using a self-aligning soldering technology. The technology is critical to package low-cost , highperforniam-e spatial light modulators (SLMs) using ferroelectric liquid crystal (FLC) over a very large scale integrated circuit (VLSI). These SLMs are important components to high-definition displays, pat tern correlation, and many other optoelectronic processors.