Teresa Bertelshofer

Explaining the short-circuit capability of SiC MOSFETs by using a simple thermal transmission-line model

In this paper the short-circuit robustness of state of the art SiC MOSFETs is analysed and their short-circuit behaviour is compared to that of a modern IGBT. A simplified thermal model of the chip itself is used to explain the difference between the behaviour of IGBT and SiC MOSFET under short-circuit conditions. Further, this model is used to derive the requirements for short-circuit detection methods for SiC MOSFETs.

A Structural Based Thermal Model Description for Vertical SiC Power MOSFETs under Fault Conditions

The accurate prediction of the SiC MOSFET withstanding time for single fault events greatly influences the requirements for device protection circuits for these devices in power converter applications, like voltage source inverters or power electronic transformers. For this reason, a thermal model, based on the structural design and the physical dimensions of the chip as well as material properties of 4H-SiC, is proposed. This article gives a general description of the thermal behaviour of vertical SiC MOSFET under various driving and boundary conditions in case of a short-circuit event. The thermal model substitutes destructive tests of a device for an individual set of boundary conditions of an occurring fault event. The validity of the analytically parametrised thermal model is verified by experimental short-circuit tests of state-of-the-art vertical SiC MOSFETs for a set of various boundary conditions. The investigated thermal model can furthermore be used to standardise different gate-oxide degradation values from the literature for means of lifetime prediction of the gate oxide for an individual application under repetitive occurring fault or overload conditions. These manufacturer specific reported values measured with no standardised testing procedures can be translated into a maximum junction temperature, which is repeatedly reached. The thermal model therefore provides a unifying parameter for the gate-oxide lifetime calculation for an individual chip and application.

Current mismatch in paralleled phases of high power SiC modules due to threshold voltage unsymmetry and different gate-driver concepts

This paper analyzes the influence of the threshold voltage on the parallel connection of three phases of a high power SiC MOSFET module. The current mismatch and the resulting switching loss distribution between paralleled phases will be investigated. Two different gate-drive circuit concepts will be tested. The influence of the choice of the gate-resistor arrangement will be presented regarding the dynamic current distribution and switching losses.

Comparing 650V and 900V SiC MOSFETs for the application in an automotive inverter

This paper researches the performance benefits of replacing the Si IGBTs and diodes in a power module for automotive drives with either 650 V or 900 V SiC MOSFETs. Evaluating the mean conduction and switching losses in a load profile allows a comparison of both voltage classes in order to show which class offers the lower overall losses in the given application. Furthermore, the influence on the switching losses of different gate driving methods and stray inductance of the commutation loops is investigated. It can be found that 900 V chips offer lower overall losses in combination with standard packages (middle to high commutation loop inductance) and standard gate driving methods (using only the gate resistance to control the switching speed). 650 V chips, however, profit from low inductive setups and smarter gate driving strategies, while at the same time displaying less oscillations during switching.