Terrence McDaniel

A 78nm 6F/sup 2/ DRAM technology for multigigabit densities

This paper discusses a manufacturable 6F/sup 2/ DRAM technology at a 78nm half-pitch feature size that results in the smallest DRAM cell size (0.036 /spl mu/m/sup 2/) to date. The novel 6F/sup 2/ cell design utilizes line/space patterning and self-aligned etches to improve process margin. An MINI capacitor that employs composite high-k dielectric materials is integrated into the process. Tungsten-clad WL and BL reduce parasitics and noise to make this 6F/sup 2/ technology suitable for 2Gb-4Gb density DRAM with a competitive die size for volume production.