Richard H. Lane

A 78nm 6F/sup 2/ DRAM technology for multigigabit densities

This paper discusses a manufacturable 6F/sup 2/ DRAM technology at a 78nm half-pitch feature size that results in the smallest DRAM cell size (0.036 /spl mu/m/sup 2/) to date. The novel 6F/sup 2/ cell design utilizes line/space patterning and self-aligned etches to improve process margin. An MINI capacitor that employs composite high-k dielectric materials is integrated into the process. Tungsten-clad WL and BL reduce parasitics and noise to make this 6F/sup 2/ technology suitable for 2Gb-4Gb density DRAM with a competitive die size for volume production.

A highly manufacturable 110 nm EDRAM process with Al/sub 2/O/sub 3/ stack MIM capacitor for cost effective high density, high speed, low voltage ASIC memory applications

A highly manufacturable 110 nm Embedded DRAM technology with stack Al/sub 2/O/sub 3/ MIM capacitor has been demonstrated successfully for the first time. High-density DRAM core with 0.1 /spl mu/m/sup 2/ cell size and high performance logic circuits have been realized at the same time by separation of the gate pattern at memory cell and peripheral logic region. Low temperature BDL process, highly reliable Al/sub 2/O/sub 3/ MIM capacitors have been developed to control process temperature. DRAM cell performance has been improved by introducing tungsten wordline, CoSi/sub 2/ plug and tungsten bitline. 7 levels Cu and CVD-OSG low-k material have been implemented to satisfy the requirement of high performance logic circuits design.