Terry Borer

The Quartus University Interface Program: enabling advanced FPGA research

FPGA researchers constantly face the challenge of determining whether their innovations will work in the real world. The Quartus University Interface Program (QUIP) allows the researcher to answer this important question by directly integrating research prototypes within one of the FPGA industrys leading CAD tool suites. This work describes the QUIP interface as well as research projects that are of significant interest to the FPGA industry.

Modular Partitioning for Incremental Compilation

This paper presents an automated partitioning strategy to divide a design into a set of partitions based on design hierarchy information. While the primary objective is to use these partitions in an incremental design flow for compile time reduction, the performance of the partitioned design should not be degraded after partitioning. Experimental results using the incremental design feature of Alteras Quartus tool show that our algorithm can generate partitioning solutions comparable with a set of manually partitioned industrial circuits and results in more than 50% compile time reduction