David Karchmer

Efficient static timing analysis and applications using edge masks

Static timing analysis (STA) with multiple clock domains and complicated exception conditions is a complex practical problem that can dramatically increase compilation time, both for back-end analysis and during place and route. In FPGA placement, timing analysis with many constraints can dominate placement run-time.In this paper we introduce a simple binary edge-mask data structure on arcs in a timing netlist which allows for efficient timing analysis in the presence of many such constraints. The technique applies to either BFS or DFS-based timing analysis. Preliminary implementations on just the basic concept show a 59% decrease in STA run-time for multi-clock designs, indicating that significant benefit is to be gained from a complete implementation. On a set of heavily constrained designs this benefit improved to 80% run-time decrease.Further applications of the edge-mask concept are shown to efficiently deal with thru-x constraints, enumerating the k-longest paths in a timing graph, and partial/incremental timing analysis aimed at significant improvements in placement time.

The Growing Complexity of FPGA CAD Tools

Summary form only given. FPGA tools have become very complex software systems. Todays FPGA tool sets include state of the art synthesis, place and route, timing analysis and power analysis tools. They also include complex graphical interfaces like floor plan and RTL viewers and system level integration tools like SOPC builder. In this article, the author gives a brief description of the history of Altera software tools. The author describes some of the key tools in the portfolio. The author also describes the development of new TimeQuest timing analyzer as a case study