Terry J. Fountain

A cellular logic array for image processing

Abstract A cellular logic image processor employing 192 cells in a 16 by 12 hexagonal array is described. The processor has been constructed and its performance assessed. The various classes of functions which can be implemented in the cellular array are discussed and sample programs explained in detail.

The CLIP7A image processor

A description is given of the CLIP7 image-processing chip. The device is implemented as a custom designed integrated circuit and contains a single processing element for use in arrays of processors. The chip uses 16-bit internal and 8-bit external data buses and divides crudely into two major sections: data processing and data input/output. The first structure to be assembled using these processors is a 256-element linear array, each element incorporating two of the CLIP7 processors. This system, known as CLIP7A, is used both to study the application of partial local autonomy techniques to image processing and also as a fast and convenient system for the emulation of other architectures. CLIP7A software and hardware are also described. >

A memory design in QCAs using the SQUARES formalism

We present a formalism for implementing circuits with quantum-dot cellular automata (QCA), comprising a set of standard circuit elements with uniform layout rules. The formalism simplifies circuit design from an engineering perspective and overcomes an observed sensitivity of QCA systems to input delays. A design for an addressable shift register is implemented, and promises considerable density gains over conventional CMOS.

The use of nanoelectronic devices in highly parallel computing systems

The continuing development of smaller electronic devices into the nanoelectronic regime offers great possibilities for the construction of highly parallel computers. This paper describes work designed to discover the best ways to take advantage of this opportunity. Simulated results are presented which indicate that improvements in clock rates of two orders of magnitude, and in packing density of three orders of magnitude, over the best current systems, should be attainable. These results apply to the class of data-parallel computers, and their attainment demands modifications to the design which are also described. Evaluation of the requirements of alternative classes of parallel architecture is currently under way, together with a study of the vitally important area of fault-tolerance.

The development of the CLIP7 image processing system

The design and construction of a new image processing system, CLIP7, is described, together with the design and operation of the custom integrated circuit on which it is based.

The propagated instruction processor

As the dimensions of electronic devices become smaller, they enter the realm of nano-electronics, where the device dimensions lie between the inter-atomic spacing (lnm) and the electron wavelength (lOnm). This offers greatly-enhanced packing density and speed of operation, but introduces the difficulty of maintaining signal quality over large distances. The paper introduces an architectural solution to this problem which is appropriate for the class of highly data-parallel computers [1,2,3]. In the propagated instruction architecture proposed here, instructions sweep across the array (and hence across the data set) in bands, one instruction following another closely. The paper examines the architectural implications of this idea, and assesses the benefits in the application area of image processing.

Enhancing the two-dimensional mesh

A number of architectures which combine efficient iconic and symbolic processing are reviewed. An approach which enhances the structure of the 2D mesh while still retaining that structure is suggested. The deficiencies of the mesh, in its usual form, in terms of symbolic processing are taken as indications of how the enhancement should proceed. The authors identify three orthogonal properties (processor power, processor autonomy, and interprocessor connectivity) which are open to manipulation. On the basis of a number of generic operations, both iconic and symbolic, the effect of varying each of these parameters is examined with emphasis on the requirements for sequences of operations to execute efficiently. An attempt is made to evaluate the cost-effectiveness of the various possibilities.<<ETX>>

An Analysis of Methods for Improving Long-Range Connectivity in Meshes

The two-dimensional mesh-connected processor array is well-suited for performing low-level image processing algorithms which involve near-neighbour operations, but poorly matched to those which are functions of data at long distances. In attempting to overcome this problem, designers of such systems have utilised a number of different schemes for adding better long-range communications to the basic mesh. Schemes which have been implemented include sets of orthogonal buses; dual-channel processors and a superimposed hypercube. Other methods which are being developed include directly switchable connections between PE input and output channels and simulated quadtree connectivity.

The CLIPS system

Abstract Two-dimensional processor arrays, such as CLIP4, have become familiar and effective solutions to many image processing problems in recent years. However, some applications require pixel resolutions far greater than that of any presently feasible array. To deal with this problem, a system (CLIP4S) has been constructed at University College London which scans a 512×4 processor array over a 512×512 pixel data area. The principal elements of interest in the system comprise the provision of data storage for sixtyfour 512×512 pixel images, hardware circuits for automatic passing of neighbourhood signals between processed sub-arrays, and the control arrangements employed.

Algorithm design for image processing in the context of cellular logic

Abstract Two novel image processing algorithms, developed within the referential framework of cellular logic neighbourhood operations, are presented. The first utilizes grey-level morphological operations to provide varying degrees of image sharpening and blurring. This is achieved by mixing the original image, the expanded image and the shrunk image under the control of a single parameter which alters the proportions of original and modified images which are mixed. The second algorithm permits optimal segmentation of an image containing more than two distinct populations of pixels, by manipulation of the grey-level histogram of the image as an image in its own right. This is implemented by morphological smoothing of the histogram image, followed by detection of minima which are uniquely defined in terms of three neighbourhood operators. Results are presented which illustrate how a result visually close to the original can be retrieved from a deliberately blurred image using the first algorithm, whilst a series of results obtained using the second algorithm show that it works well for images in which the pixel populations are well-separated, but poorly if the populations are too small to survive the histogram smoothing step.